Shirshendu Das

Publication Activity (10 Years)

Years Active: 2013-2024
Publications (10 Years): 38

Top Topics

Top Venues

J. Syst. Archit.

Publications

Aditya S. Gangwar, Prathamesh Nitin Tanksale, Shirshendu Das, Sudeepta Mishra
$\mathcal{F}lush+early\mathcal{R}\text{ELOAD}$: Covert Channels Attack on Shared LLC Using MSHR Merging. DATE (2024)
Jaspinder Kaur, Shirshendu Das
RSPP: Restricted Static Pseudo-Partitioning for Mitigation of Cross-Core Covert Channel Attacks. ACM Trans. Design Autom. Electr. Syst. 29 (2) (2024)
Divyansh Maura, Tanmay Goel, Kaustav Goswami, Dip Sankar Banerjee, Shirshendu Das
Variation aware power management for GPU memories. Microprocess. Microsystems 96 (2023)
Atul Kumar, Dipika Deb, Shirshendu Das, Palash Das
edAttack: Hardware Trojan Attack on On-Chip Packet Compression. IEEE Des. Test 40 (6) (2023)
Jaspinder Kaur, Shirshendu Das
TPPD: Targeted Pseudo Partitioning based Defence for cross-core covert channel attacks. J. Syst. Archit. 135 (2023)
Jaspinder Kaur, Shirshendu Das
ACPC: Covert Channel Attack on Last Level Cache using Dynamic Cache Partitioning. ISQED (2023)
Kaustav M. Goswami, Shirshendu Das, Sagar Satapathy, Dip Sankar Banerjee
A Case for Amplifying Row Hammer Attacks via Cell-Coupling in DRAM Devices. MEMSYS (2022)
Bindu Agarwalla, Shirshendu Das, Nilkanta Sahu
Process variation aware DRAM-Cache resizing. J. Syst. Archit. 123 (2022)
Bharat Bisht, Shirshendu Das
BHT-NoC: Blaming Hardware Trojans in NoC Routers. IEEE Des. Test 39 (6) (2022)
Jaspinder Kaur, Shirshendu Das
TPPD: Targeted Pseudo Partitioning based Defence for Cross-Core Covert Channel Attacks. CoRR (2022)
Bindu Agarwalla, Nilkanta Sahu, Shirshendu Das
PV-aware Replacement Policy for Two-level Shared Cache. iSES (2022)
Sudershan Kumar, Prabuddha Sinha, Shirshendu Das
WinDRAM: Weak rows as in-DRAM cache. Concurr. Comput. Pract. Exp. 34 (28) (2022)
Samiksha Verma, Shirshendu Das, Vipul Bondre
Hybrid Refresh: Improving DRAM Performance by Handling Weak Rows Smartly. MEMSYS (2022)
Kaustav Goswami, Hemanta Kumar Mondal, Shirshendu Das, Dip Sankar Banerjee
VAR-DRAM: Variation-Aware Framework for Efficient Dynamic Random Access Memory Design. CoRR (2022)
Shobhit Kumar, Shirshendu Das, Manaal Mukhtar Jamadar, Jaspinder Kaur
Efficient On-chip Communication for Neuromorphic Systems. SmartWorld/SCALCOM/UIC/ATC/IOP/SCI (2021)
Manaal Mukhtar Jamadar, Jaspinder Kaur, Shirshendu Das
MAPCP: Memory Access Pattern Classifying Prefetcher. MEMSYS (2021)
Kaustav Goswami, Dip Sankar Banerjee, Shirshendu Das
Towards Enhanced System Efficiency while Mitigating Row Hammer. ACM Trans. Archit. Code Optim. 18 (4) (2021)
Anurag Agarwal, Jaspinder Kaur, Shirshendu Das
Exploiting Secrets by Leveraging Dynamic Cache Partitioning of Last Level Cache. DATE (2021)
Bindu Agarwalla, Shirshendu Das, Nilkanta Sahu
Efficient Cache Resizing policy for DRAM-based LLCs in ChipMultiprocessors. J. Syst. Archit. 113 (2021)
Kousik Kumar Dutta, Prathamesh Nitin Tanksale, Shirshendu Das
A Fairness Conscious Cache Replacement Policy for Last Level Cache. DATE (2021)
Tanmay Goel, Divyansh Maura, Kaustav Goswami, Shirshendu Das, Dip Sankar Banerjee
Towards Row Sensitive DRAM Refresh through Retention Awareness. ISQED (2021)
Jaspinder Kaur, Shirshendu Das
A Survey on Cache Timing Channel Attacks for Multicore Processors. J. Hardw. Syst. Secur. 5 (2) (2021)
Dipika Deb, John Jose, Shirshendu Das, Hemangee K. Kapoor
Cost effective routing techniques in 2D mesh NoC using on-chip transmission lines. J. Parallel Distributed Comput. 123 (2019)
Kaustav Goswami, Hemanta Kumar Mondal, Shirshendu Das, Dip Sankar Banerjee
State Preserving Dynamic DRAM Bank Re-Configurations for Enhanced Power Efficiency. ISQED (2019)
Alankar V. Umdekar, Arijit Nath, Shirshendu Das, Hemangee K. Kapoor
Dynamic Thermal Management by Using Task Migration in Conjunction with Frequency Scaling for Chip Multiprocessors. VLSI Design (2018)
Shirshendu Das, Hemangee K. Kapoor
Dynamic Associativity Management in Tiled CMPs by Runtime Adaptation of Fellow Sets. IEEE Trans. Parallel Distributed Syst. 28 (8) (2017)
Shirshendu Das, Hemangee K. Kapoor
Latency Aware Block Replacement for L1 Caches in Chip Multiprocessor. ISVLSI (2017)
Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor
Static energy efficient cache reconfiguration for dynamic NUCA in tiled CMPs. SAC (2016)
Shirshendu Das, Hemangee K. Kapoor
Towards a Better Cache Utilization by Selective Data Storage for CMP Last Level Caches. VLSI Design (2016)
Surajit Das, Shirshendu Das, Hemangee K. Kapoor
Tag only storage for capacity optimised last level cache in chip multiprocessors. VDAT (2016)
Shirshendu Das, Hemangee K. Kapoor
Dynamic associativity enabled DNUCA to improve block localisation in tiled CMPs. SAC (2016)
Shirshendu Das, Hemangee K. Kapoor
A Framework for Block Placement, Migration, and Fast Searching in Tiled-DNUCA Architecture. ACM Trans. Design Autom. Electr. Syst. 22 (1) (2016)
Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor
Power aware cache miss reduction by energy efficient victim retention. VDAT (2015)
Kartheek Vanapalli, Hemangee K. Kapoor, Shirshendu Das
An efficient searching mechanism for dynamic NUCA in chip multiprocessors. VDAT (2015)
Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor
Performance Constrained Static Energy Reduction Using Way-Sharing Target-Banks. IPDPS Workshops (2015)
Hemangee K. Kapoor, Shirshendu Das, Shounak Chakraborty
Static energy reduction by performance linked cache capacity management in tiled CMPs. SAC (2015)
Shirshendu Das, Hemangee K. Kapoor
Exploration of Migration and Replacement Policies for Dynamic NUCA over Tiled CMPs. VLSI Design (2015)
Shirshendu Das, Hemangee K. Kapoor
Dynamic associativity management using utility based way-sharing. SAC (2015)
Shirshendu Das, Hemangee K. Kapoor
Victim retention for reducing cache misses in tiled chip multiprocessors. Microprocess. Microsystems 38 (4) (2014)
B. Venkateswarlu Naik, Shirshendu Das, Hemangee K. Kapoor
RT-DVS for Power Optimization in Multiprocessor Real-Time Systems. ICIT (2014)
M. Lakshmi Prasad, Shirshendu Das, Hemangee K. Kapoor
An Approach for Multicast Routing in Networks-on-Chip. ICIT (2014)
Shirshendu Das, Hemangee K. Kapoor
Dynamic Associativity Management Using Fellow Sets. ISED (2013)
Shirshendu Das, Parasara Sridhar Duggirala, Hemangee K. Kapoor
A formal framework for interfacing mixed-timing systems. Integr. 46 (3) (2013)
Shirshendu Das, Nagaraju Polavarapu, Prateek D. Halwe, Hemangee K. Kapoor
Random-LRU: A Replacement Policy for Chip Multiprocessors. VDAT (2013)
Hemangee K. Kapoor, Praveen Kanakala, Malti Verma, Shirshendu Das
Design and formal verification of a hierarchical cache coherence protocol for NoC based multiprocessors. J. Supercomput. 65 (2) (2013)
Prateek D. Halwe, Shirshendu Das, Hemangee K. Kapoor
Towards a Better Cache Utilization Using Controlled Cache Partitioning. DASC (2013)