Latency Aware Block Replacement for L1 Caches in Chip Multiprocessor.
Shirshendu DasHemangee K. KapoorPublished in: ISVLSI (2017)
Keyphrases
- access latency
- replacement policy
- memory access
- memory bandwidth
- level parallelism
- low cost
- high speed
- low latency
- scheduling algorithm
- prefetching
- multithreading
- response time
- analog vlsi
- physical design
- highly parallel
- single chip
- high density
- programmable logic
- multiprocessor systems
- caching scheme
- evolvable hardware
- data access
- circuit design
- distributed memory