Gary S. Tyson

Publication Activity (10 Years)

Years Active: 1992-2020
Publications (10 Years): 3

Top Topics

Friendly Interface

Practical Experience

Benchmark Suite

Computer Engineering

Top Venues

IEEE Comput. Archit. Lett.

Publications

An-I Andy Wang, David B. Whalley, Zhenghao Zhang, Gary S. Tyson
Experience of Administering Our First S-STEM Program to Broaden Participation in Computer Science. SIGCSE (2020)
Zachary Yannes, Gary S. Tyson
Amniote: A User Space Interface to the Android Runtime. ENASE (2019)
Martin K. Brown, Zachary Yannes, Michael Lustig, Mazdak Sanati, Sally A. McKee, Gary S. Tyson, Steven K. Reinhardt
Agave: A benchmark suite for exploring the complexities of the Android software stack. ISPASS (2016)
B. Davis, Ryan Baird, Peter Gavin, Magnus Själander, Ian Finlayson, F. Rasapour, G. Cook, Gang-Ryung Uh, David B. Whalley, Gary S. Tyson
Scheduling instruction effects for a statically pipelined processor. CASES (2015)
An-I Andy Wang, Gary S. Tyson, David B. Whalley, Robert van Engelen, Zhenghao Zhang
A journey toward obtaining our first NSF S-STEM (scholarship) grant. SIGCSE (2014)
Ian Finlayson, Brandon Davis, Peter Gavin, Gang-Ryung Uh, David B. Whalley, Magnus Själander, Gary S. Tyson
Improving processor efficiency by statically pipelining instructions. LCTES (2013)
Daniel Chang, Stephen Hines, Paul E. West, Gary S. Tyson, David B. Whalley
Program Differentiation. J. Circuits Syst. Comput. 21 (2) (2012)
Ian Finlayson, Gang-Ryung Uh, David B. Whalley, Gary S. Tyson
An Overview of Static Pipelining. IEEE Comput. Archit. Lett. 11 (1) (2012)
Ian Finlayson, Gang-Ryung Uh, David B. Whalley, Gary S. Tyson
Improving Low Power Processor Efficiency with Static Pipelining. Interaction between Compilers and Computer Architectures (2011)
Michael Mitchell, Christopher R. Meyers, An-I Andy Wang, Gary S. Tyson
ContextProvider: Context awareness for medical monitoring applications. EMBC (2011)
Yue Li, Gary S. Tyson, Jinfeng Zhang
Effect of sequences on the shape of protein energy landscapes. BCB (2010)
Prasad A. Kulkarni, David B. Whalley, Gary S. Tyson, Jack W. Davidson
Practical exhaustive optimization phase order exploration and evaluation. ACM Trans. Archit. Code Optim. 6 (1) (2009)
Major Bhadauria, Sally A. McKee, Karan Singh, Gary S. Tyson
Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems. Trans. High Perform. Embed. Archit. Compil. 2 (2009)
Paul E. West, Yuval Peress, Gary S. Tyson, Sally A. McKee
Core monitors: monitoring performance in multicore processors. Conf. Computing Frontiers (2009)
Stephen Roderick Hines, Yuval Peress, Peter Gavin, David B. Whalley, Gary S. Tyson
Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE). LCTES (2009)
Renato J. O. Figueiredo, P. Oscar Boykin, José A. B. Fortes, Tao Li, Jie-Kwon Peir, David Wolinsky, Lizy K. John, David R. Kaeli, David J. Lilja, Sally A. McKee, Gokhan Memik, Alain Roy, Gary S. Tyson
Archer: A Community Distributed Computing Infrastructure for Computer Architecture Research and Education. CollaborateCom (2008)
Renato J. O. Figueiredo, P. Oscar Boykin, José A. B. Fortes, Tao Li, Jie-Kwon Peir, David Wolinsky, Lizy Kurian John, David R. Kaeli, David J. Lilja, Sally A. McKee, Gokhan Memik, Alain Roy, Gary S. Tyson
Archer: A Community Distributed Computing Infrastructure for Computer Architecture Research and Education CoRR (2008)
David B. Whalley, Gary S. Tyson
Enhancing the effectiveness of utilizing an instruction register file. IPDPS (2008)
Christopher Zimmer, Stephen Roderick Hines, Prasad A. Kulkarni, Gary S. Tyson, David B. Whalley
Facilitating compiler optimizations through the dynamic mapping of alternate register structures. CASES (2007)
Stephen Hines, David B. Whalley, Gary S. Tyson
Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache. MICRO (2007)
Michael J. Geiger, Sally A. McKee, Gary S. Tyson
Specializing Cache Structures for High Performance and Energy Conservation in Embedded Systems. Trans. High Perform. Embed. Archit. Compil. 1 (2007)
Stephen Roderick Hines, Gary S. Tyson, David B. Whalley
Addressing instruction fetch bottlenecks by using an instruction register file. LCTES (2007)
Major Bhadauria, Sally A. McKee, Karan Singh, Gary S. Tyson
Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems. HiPEAC (2007)
Prasad A. Kulkarni, David B. Whalley, Gary S. Tyson
Evaluating Heuristic Optimization Phase Order Search Algorithms. CGO (2007)
Prasad A. Kulkarni, David B. Whalley, Gary S. Tyson, Jack W. Davidson
Exhaustive Optimization Phase Order Space Exploration. CGO (2006)
William C. Kreahling, Stephen Hines, David B. Whalley, Gary S. Tyson
Reducing the cost of conditional transfers of control by using comparison specifications. LCTES (2006)
Prasad A. Kulkarni, David B. Whalley, Gary S. Tyson, Jack W. Davidson
In search of near-optimal optimization phase orderings. LCTES (2006)
Allen C. Cheng, Gary S. Tyson
High-quality ISA synthesis for low-power cache designs in embedded microprocessors. IBM J. Res. Dev. 50 (2-3) (2006)
Stephen Hines, David B. Whalley, Gary S. Tyson
Adapting compilation techniques to enhance the packing of instructions into registers. CASES (2006)
Michael J. Geiger, Sally A. McKee, Gary S. Tyson
Drowsy region-based caches: minimizing both dynamic and static power dissipation. Conf. Computing Frontiers (2005)
Stephen Hines, Gary S. Tyson, David B. Whalley
Reducing Instruction Fetch Cost by Packing Instructions into RegisterWindows. MICRO (2005)
Stephen Hines, Joshua Green, Gary S. Tyson, David B. Whalley
Improving Program Efficiency by Packing Instructions into Registers. ISCA (2005)
Allen C. Cheng, Gary S. Tyson
An Energy Efficient Instruction Set Synthesis Framework for Low Power Embedded System Designs. IEEE Trans. Computers 54 (6) (2005)
Allen C. Cheng, Gary S. Tyson, Trevor N. Mudge
PowerFITS: Reduce Dynamic and Static I-Cache Power Using Application Specific Instruction Set Synthesis. ISPASS (2005)
Michael J. Geiger, Sally A. McKee, Gary S. Tyson
Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation. HiPEAC (2005)
Allen C. Cheng, Gary S. Tyson, Trevor N. Mudge
FITS: framework-based instruction-set tuning synthesis for embedded application specific processors. DAC (2004)
Viji Srinivasan, Edward S. Davidson, Gary S. Tyson
A Prefetch Taxonomy. IEEE Trans. Computers 53 (2) (2004)
Edward S. Tam, Stevan A. Vlaovic, Gary S. Tyson, Edward S. Davidson
Allocation by Conflict: A Simple Effective Multilateral Cache Management Scheme. ICCD (2001)
Hsien-Hsin S. Lee, Mikhail Smelyanskiy, Chris J. Newburn, Gary S. Tyson
Stack Value File: Custom Microarchitecture for the Stack. HPCA (2001)
Viji Srinivasan, Edward S. Davidson, Gary S. Tyson, Mark J. Charney, Thomas R. Puzak
Branch History Guided Instruction Prefetching. HPCA (2001)
Hsien-Hsin S. Lee, Gary S. Tyson, Matthew K. Farrens
Improving Bandwidth Utilization using Eager Writeback. J. Instr. Level Parallelism 3 (2001)
Stevan A. Vlaovic, Edward S. Davidson, Gary S. Tyson
Improving BTB performance in the presence of DLLs. MICRO (2000)
Hsien-Hsin S. Lee, Gary S. Tyson, Matthew K. Farrens
Eager writeback - a technique for improving bandwidth utilization. MICRO (2000)
Murali Annavaram, Gary S. Tyson, Edward S. Davidson
Instruction overhead and data locality effects in superscalar processors. ISPASS (2000)
Mikhail Smelyanskiy, Gary S. Tyson, Edward S. Davidson
Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining. IEEE PACT (2000)
Hsien-Hsin S. Lee, Gary S. Tyson
Region-based caching: an energy-delay efficient memory architecture for embedded processors. CASES (2000)
Krisztián Flautner, Gary S. Tyson, Trevor N. Mudge
A high level simulator integrated with the Mirv compiler. SIGARCH Comput. Archit. News 27 (1) (1999)
Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson
Active Management of Data Caches by Exploiting Reuse Information. IEEE Trans. Computers 48 (11) (1999)
Matt Postiff, Gary S. Tyson, Trevor N. Mudge
Performance Limits of Trace Caches. J. Instr. Level Parallelism 1 (1999)
Matthew A. Postiff, David A. Greene, Gary S. Tyson, Trevor N. Mudge
The limits of instruction level parallelism in SPEC95 applications. SIGARCH Comput. Archit. News 27 (1) (1999)
Gary S. Tyson, Todd M. Austin
Memory Renaming: Fast, Early and Accurate Processing of Memory Communication. Int. J. Parallel Program. 27 (5) (1999)
Glenn Reinman, Brad Calder, Dean M. Tullsen, Gary S. Tyson, Todd M. Austin
Classifying load and store instructions for memory renaming. International Conference on Supercomputing (1999)
Edward S. Tam, Jude A. Rivers, Gary S. Tyson, Edward S. Davidson
mlcache: A Flexible Multi-Lateral Cache Simulator. MASCOTS (1998)
Sangwook P. Kim, Gary S. Tyson
Analyzing the Working Set Characteristics of Branch Execution. MICRO (1998)
Gary S. Tyson, Steven K. Reinhardt, Trevor N. Mudge
Computer architecture instruction at the University of Michigan. WCAE@ISCA (1998)
Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson
Evaluating the performance of active cache management schemes. ICCD (1998)
Jude A. Rivers, Edward S. Tam, Gary S. Tyson, Edward S. Davidson, Matthew K. Farrens
Utilizing Reuse Information in Data Cache Management. International Conference on Supercomputing (1998)
Gary S. Tyson, Todd M. Austin
Improving the Accuracy and Performance of Memory Communication Through Renaming. MICRO (1997)
Gary S. Tyson, Matthew K. Farrens, John Matthews, Andrew R. Pleszkun
Managing data caches using selective cache line replacement. Int. J. Parallel Program. 25 (3) (1997)
Jude A. Rivers, Gary S. Tyson, Edward S. Davidson, Todd M. Austin
On High-Bandwidth Data Cache Design for Multi-Issue Processors. MICRO (1997)
Gary S. Tyson, Matthew K. Farrens
Evaluating the Effects of Predicated Execution on Branch Prediction. Int. J. Parallel Program. 24 (2) (1996)
Gary S. Tyson, Matthew K. Farrens, John Matthews, Andrew R. Pleszkun
A modified approach to data cache management. MICRO (1995)
Gary S. Tyson
The effects of predicated execution on branch prediction. MICRO (1994)
Matthew K. Farrens, Gary S. Tyson, Andrew R. Pleszkun
A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors. ISCA (1994)
Gary S. Tyson, Matthew K. Farrens
Code scheduling for multiple instruction stream architectures. Int. J. Parallel Program. 22 (3) (1994)
Gary S. Tyson, Matthew K. Farrens
Techniques for extracting instruction level parallelism on MIMD architectures. MICRO (1993)
Matthew K. Farrens, Arvin Park, Gary S. Tyson
Modifying VM hardware to reduce address pin requirements. MICRO (1992)
Matthew K. Farrens, Arvin Park, Rob Fanfelle, Pius Ng, Gary S. Tyson
A partitioned translation lookaside buffer approach to reducing address bandwith. ISCA (1992)
Gary S. Tyson, Matthew K. Farrens, Andrew R. Pleszkun
MISC: a Multiple Instruction Stream Computer. MICRO (1992)