Edward S. Davidson

Publication Activity (10 Years)

Years Active: 1968-2014
Publications (10 Years): 0

Top Topics

Scheduling Problem

Search Algorithm

Functional Requirements

Top Venues

ICS 25th Anniversary

Publications

Alexandre E. Eichenberger, Edward S. Davidson, Santosh G. Abraham
Author retrospective for optimum modulo schedules for minimum register requirements. ICS 25th Anniversary (2014)
Michel N. Victor, Aris K. Silzars, Edward S. Davidson
A freespace crossbar for multi-core processors. ICS (2008)
Mikhail Smelyanskiy, Scott A. Mahlke, Edward S. Davidson
Probabilistic Predicate-Aware Modulo Scheduling. CGO (2004)
Viji Srinivasan, Edward S. Davidson, Gary S. Tyson
A Prefetch Taxonomy. IEEE Trans. Computers 53 (2) (2004)
Mikhail Smelyanskiy, Scott A. Mahlke, Edward S. Davidson, Hsien-Hsin S. Lee
Predicate-Aware Scheduling: A Technique for Reducing Resource Constraints. CGO (2003)
Murali Annavaram, Jignesh M. Patel, Edward S. Davidson
Call graph prefetching for database applications. ACM Trans. Comput. Syst. 21 (4) (2003)
Stevan A. Vlaovic, Edward S. Davidson
Boosting trace cache performance with nonhead miss speculation. ICS (2002)
Stevan A. Vlaovic, Edward S. Davidson
TAXI: Trace Analysis for X86 Interpretation. ICCD (2002)
Edward S. Tam, Stevan A. Vlaovic, Gary S. Tyson, Edward S. Davidson
Allocation by Conflict: A Simple Effective Multilateral Cache Management Scheme. ICCD (2001)
Murali Annavaram, Jignesh M. Patel, Edward S. Davidson
Call Graph Prefetching for Database Applications. HPCA (2001)
Murali Annavaram, Jignesh M. Patel, Edward S. Davidson
Data prefetching by dependence graph precomputation. ISCA (2001)
Viji Srinivasan, Edward S. Davidson, Gary S. Tyson, Mark J. Charney, Thomas R. Puzak
Branch History Guided Instruction Prefetching. HPCA (2001)
G. X. Tyson, M. Smelyanskyi, Edward S. Davidson
Evaluating the Use of Register Queues in Software Pipelined Loops. IEEE Trans. Computers 50 (8) (2001)
Stevan A. Vlaovic, Edward S. Davidson, Gary S. Tyson
Improving BTB performance in the presence of DLLs. MICRO (2000)
Murali Annavaram, Gary S. Tyson, Edward S. Davidson
Instruction overhead and data locality effects in superscalar processors. ISPASS (2000)
Mikhail Smelyanskiy, Gary S. Tyson, Edward S. Davidson
Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining. IEEE PACT (2000)
Waleed Meleis, Edward S. Davidson
Dual-Issue Scheduling with Spills for Binary Trees. SODA (1999)
Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson
Active Management of Data Caches by Exploiting Reuse Information. IEEE Trans. Computers 48 (11) (1999)
Arthur W. Burks, Edward S. Davidson
Introduction to "The ENIAC". Proc. IEEE 87 (6) (1999)
David J. Kuck, Edward S. Davidson, Duncan H. Lawrie, Ahmed H. Sameh, Chuan-Qi Zhu
The Cedar System and an Initial Performance Study. 25 Years ISCA: Retrospectives and Reprints (1998)
Edward S. Tam, Jude A. Rivers, Gary S. Tyson, Edward S. Davidson
mlcache: A Flexible Multi-Lateral Cache Simulator. MASCOTS (1998)
Gheith A. Abandah, Edward S. Davidson
Configuration Independent Analysis for Characterizing Shared-Memory Applications. IPPS/SPDP (1998)
Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson
Evaluating the performance of active cache management schemes. ICCD (1998)
Gheith A. Abandah, Edward S. Davidson
Origin 2000 Design Enhancements for Communication Intensive Applications. IEEE PACT (1998)
Alexander V. Veidenbaum, Pen-Chung Yew, David J. Kuck, Constantine D. Polychronopoulos, David A. Padua, Edward S. Davidson, Kyle A. Gallivan
Retrospective: The Cedar System. 25 Years ISCA: Retrospectives and Reprints (1998)
Gheith A. Abandah, Edward S. Davidson
Effects of Architectural and Technological Advances on the HP/Convex Exemplar's Memory and Communication Performance. ISCA (1998)
Janak H. Patel, Edward S. Davidson
Improving the Throughput of a Pipeline by Insertion of Delays. 25 Years ISCA: Retrospectives and Reprints (1998)
Gheith A. Abandah, Edward S. Davidson
Characterizing Distributed Shared Memory Performance: A Case Study of the Convex SPP1000. IEEE Trans. Parallel Distributed Syst. 9 (2) (1998)
Jude A. Rivers, Edward S. Tam, Gary S. Tyson, Edward S. Davidson, Matthew K. Farrens
Utilizing Reuse Information in Data Cache Management. International Conference on Supercomputing (1998)
Alexandre E. Eichenberger, Edward S. Davidson
Efficient Formulation for Optimal Modulo Schedulers. PLDI (1997)
Jude A. Rivers, Edward S. Tam, Edward S. Davidson
On Effective Data Supply For Multi-Issue Processors. ICCD (1997)
Jude A. Rivers, Gary S. Tyson, Edward S. Davidson, Todd M. Austin
On High-Bandwidth Data Cache Design for Multi-Issue Processors. MICRO (1997)
Jude A. Rivers, Edward S. Davidson
Reducing Conflicts in Direct-Mapped Caches with a Temporality-Based Design. ICPP, Vol. 1 (1996)
Alexandre E. Eichenberger, Edward S. Davidson, Santosh G. Abraham
Minimizing Register Requirements of a Modulo Schedule via Optimum Stage Scheduling. Int. J. Parallel Program. 24 (2) (1996)
Alexandre E. Eichenberger, Edward S. Davidson
A Reduced Multipipeline Machine Description that Preserves Scheduling Constraints. PLDI (1996)
Gheith A. Abandah, Edward S. Davidson
Modeling the Communication Performance of the IBM SP2. IPPS (1996)
Karen A. Tomko, Edward S. Davidson
Profile Driven Weighted Decomposition. International Conference on Supercomputing (1996)
Jude A. Rivers, Edward S. Davidson
Performance Issues in Integrating Temporality-Based Caching with Prefetching. Perform. Evaluation (4) (1996)
Alexandre E. Eichenberger, Edward S. Davidson
Stage scheduling: a technique to reduce the register requirements of a modulo schedule. MICRO (1995)
Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah
Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (12) (1995)
John-David Wellman, Edward S. Davidson
The resource conflict methodology for early-stage design space exploration of superscalar RISC processors. ICCD (1995)
Alexandre E. Eichenberger, Edward S. Davidson
Register allocation for predicated code. MICRO (1995)
Alexandre E. Eichenberger, Edward S. Davidson, Santosh G. Abraham
Optimum Modulo Schedules for Minimum Register Requirements. International Conference on Supercomputing (1995)
Waleed Meleis, Edward S. Davidson
Optimal local register allocation for a multiple-issue machine. International Conference on Supercomputing (1994)
Tien-Pao Shih, Edward S. Davidson
Grouping Array Layouts to Reduce Communication and Improve Locality of Parallel Programs. ICPADS (1994)
Eric L. Boyd, Edward S. Davidson
Communication in the KSR1 MPP: performance evaluation using synthetic workload experiments. International Conference on Supercomputing (1994)
Alexandre E. Eichenberger, Edward S. Davidson, Santosh G. Abraham
Minimum register requirements for a modulo schedule. MICRO (1994)
Eric L. Boyd, Waqar Azeem, Hsien-Hsin S. Lee, Tien-Pao Shih, Shih-Hao Hung, Edward S. Davidson
A Hierarchical Approach to Modeling and Improving the Performance of Scientific Applications on the KSR1. ICPP (3) (1994)
Daniel Windheiser, Eric L. Boyd, Eric Hao, Santosh G. Abraham, Edward S. Davidson
KSR 1 Multiprocessor: Analysis of Latency Hiding Techniques in a Sparse Solver. IPPS (1993)
David J. Kuck, Edward S. Davidson, Duncan H. Lawrie, Ahmed H. Sameh, Chuan-Qi Zhu, Alexander V. Veidenbaum, Jeff Konicek, Pen-Chung Yew, Kyle A. Gallivan, William Jalby, Harry A. G. Wijshoff, Randall Bramley, Ulrike Meier Yang, Perry A. Emrath, David A. Padua, Rudolf Eigenmann, Jay P. Hoeflinger, Greg P. Jaxon, Zhiyuan Li, T. Murphy, John T. Andrews, Stephen W. Turner
The Cedar System and an Initial Performance Study. ISCA (1993)
William H. Mangione-Smith, Tien-Pao Shih, Santosh G. Abraham, Edward S. Davidson
Approaching a machine-application bound in delivered performance on scientific code. Proc. IEEE 81 (8) (1993)
Eric L. Boyd, Edward S. Davidson
Hierarchical Performance Modeling with MACS: A Case Study of the Convex C-240. ISCA (1993)
Eric L. Boyd, John-David Wellman, Santosh G. Abraham, Edward S. Davidson
Evaluating the Communication Performance of MPPs Using Synthetic Sparse Matrix Multiplication Workloads. International Conference on Supercomputing (1993)
Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson
Synchronization of pipelines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (8) (1993)
Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah
Using constraint geometry to determine maximum rate pipeline clocking. ICCAD (1992)
William H. Mangione-Smith, Santosh G. Abraham, Edward S. Davidson
Register requirements of pipelined processors. ICS (1992)
Jarir K. Chaar, Richard A. Volz, Edward S. Davidson
An integrated approach to developing manufacturing control software. ICRA (1991)
William H. Mangione-Smith, Santosh G. Abraham, Edward S. Davidson
A Performance Comparison of the IBM RS/6000 and the Astronautics ZS-1. Computer 24 (1) (1991)
Jeff Konicek, Tracy Tilton, Alexander V. Veidenbaum, Chuan-Qi Zhu, Edward S. Davidson, Ruppert A. Downing, Michael J. Haney, Manish Sharma, Pen-Chung Yew, P. Michael Farmwald, David J. Kuck, Daniel M. Lavery, Robert A. Lindsey, D. Pointer, John T. Andrews, Thomas Beck, T. Murphy, Stephen W. Turner, Nancy J. Warter
The Organization of the Cedar System. ICPP (1) (1991)
Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson
Optimal Clocking of Circular Pipelines. ICCD (1991)
William H. Mangione-Smith, Santosh G. Abraham, Edward S. Davidson
Vector Register Design for Polycyclic Vector Scheduling. ASPLOS (1991)
Jarir K. Chaar, Edward S. Davidson
Cyclic job shop scheduling using reservation tables. ICRA (1990)
J. H. Tang, Edward S. Davidson, J. Tong
Polycyclic Vector scheduling vs. Chaining on 1-Port Vector supercomputers. SC (1988)
J. H. Tang, Edward S. Davidson
An evaluation of Cray X-MP performance on vectorizable Livermore FORTRAN kernels. ICS (1988)
Geoffrey D. McNiven, Edward S. Davidson
Analysis of Memory Referencing Behavior For Design of Local Memories. ISCA (1988)
Timothy A. Davis, Edward S. Davidson
Pairwise Reduction for the Direct, Parallel Solution of Sparse, Unsymmetric Sets of Linear Equations. IEEE Trans. Computers 37 (12) (1988)
Timothy A. Davis, Edward S. Davidson
PSOLVE : A Concurrent Algorithm for Solving Sparse Systems of Linear Equations. ICPP (1987)
Philip G. Emma, Edward S. Davidson
Characterization of Branch and Data Dependencies in Programs for Evaluating Pipeline Performance. IEEE Trans. Computers 36 (7) (1987)
Santosh G. Abraham, Edward S. Davidson
A Communication Model for Optimizing Hierarchical Multiprocessor Systems. ICPP (1986)
Edward S. Davidson
A Broader Range of Possible Answers to the Issues Raised by RISC. COMPCON (1986)
Andrew R. Pleszkun, Gurindar S. Sohi, Bassam Z. Kahhaleh, Edward S. Davidson
Features of the Structured Memory Access (SMA) Architecture. COMPCON (1986)
Peter Y.-T. Hsu, Edward S. Davidson
Highly Concurrent Scalar Processing. ISCA (1986)
W. K. Jenkins, Edward S. Davidson, D. F. Paul
A custom-designed integrated circuit for the realization of residue number digital filters. ICASSP (1985)
Peter Y.-T. Hsu, Joseph T. Rahmeh, Edward S. Davidson, Jacob A. Abraham
TIDBITS: Speedup Via Time-Delay Bit-Slicing in ALU Design for VLSI Technology. ISCA (1985)
Gurindar S. Sohi, Edward S. Davidson, Janak H. Patel
An Efficient LISP-Execution Architecture with a New Representation for List Structures. ISCA (1985)
Pradip Bose, Edward S. Davidson
Design of Instruction Set Architectures for Support of High-Level Languages . ISCA (1984)
Phil C. C. Yeh, Janak H. Patel, Edward S. Davidson
Shared Cache for Multiple-Stream Computer Systems. IEEE Trans. Computers 32 (1) (1983)
Andrew R. Pleszkun, Edward S. Davidson
Structured Memory Access Architecture. ICPP (1983)
Phil C. C. Yeh, Janak H. Patel, Edward S. Davidson
Performance of Shared Cache for Parallel-Pipelined Computer Systems ISCA (1983)
David W. L. Yen, Janak H. Patel, Edward S. Davidson
Memory Interference in Synchronous Multiprocessor Systems. IEEE Trans. Computers 31 (11) (1982)
Edward S. Davidson
Evaluating database management systems. AFIPS National Computer Conference (1982)
Robert L. Budzinski, Edward S. Davidson, Wataru Mayeda, Harold S. Stone
DMIN: An Algorithm for Computing the Optimal Dynamic Allocation in a Virtual Memory Computer. IEEE Trans. Software Eng. 7 (1) (1981)
Robert L. Budzinski, Edward S. Davidson
A Comparison of Dynamic and Static Virtual Memory Allocation Algorithms. IEEE Trans. Software Eng. 7 (1) (1981)
B. Kumar, Edward S. Davidson
Computer System Design Using a Hierarchical Approach to Performance Evaluation. Commun. ACM 23 (9) (1980)
Edward S. Davidson
A Multiple Stream Microprocessor Prototype System: AMP-1. ISCA (1980)
W. J. Kaminsky, Edward S. Davidson
Special Feature: Developing a Multiple-Instruction-Stream Single-Chip Processor. Computer 12 (12) (1979)
B. Kumar, Edward S. Davidson
Performance Evaluation of Highly Concurrent Computers by Deterministic Simulation. Commun. ACM 21 (11) (1978)
Dan W. Hammerstrom, Edward S. Davidson
Information Content of CPU Memory Referencing Behavior. ISCA (1977)
Faye A. Briggs, Edward S. Davidson
Organization of Semiconductor Memories for Parallel-Pipelined Processors. IEEE Trans. Computers 26 (2) (1977)
Janak H. Patel, Edward S. Davidson
Improving the Throughput of a Pipeline by Insertion of Delays. ISCA (1976)
Leonard E. Shar, Edward S. Davidson
A multiminiprocessor system implemented through pipelining. Computer 7 (2) (1974)
Hsien-Hsin S. Lee, Edward S. Davidson
Redundancy Testing in Combinational Networks. IEEE Trans. Computers 23 (10) (1974)
Daniel L. Weller, Edward S. Davidson
Optimal Searching Algorithms for Parallel Pipelined Computers. Sagamore Computer Conference (1974)
Hsiao-Peng Lee, Edward S. Davidson
A Transform for NAND Network Design. IEEE Trans. Computers 21 (1) (1972)
Hsiao P. Lee, Edward S. Davidson
Comments on "A Minimization Technique for TANT Networks". IEEE Trans. Computers 21 (4) (1972)
Edward S. Davidson
An Algorithm for NAND Decomposition Under Network Constraints. IEEE Trans. Computers 18 (12) (1969)
Edward S. Davidson, Gernot Metze
. IEEE Trans. Computers 18 (9) (1969)
Edward S. Davidson, Gernot Metze
Comments on "An Algorithm for Synthesis of Multiple-Output Combinational Logic". IEEE Trans. Computers 17 (11) (1968)