Joseph T. Rahmeh

Publication Activity (10 Years)

Years Active: 1985-1993
Publications (10 Years): 0

Publications

Dah-Cherng Yuan, Lawrence T. Pillage, Joseph T. Rahmeh
Evaluation of Parts by Mixed-Level DC-Connected Components in Logic Simulation. DAC (1993)
Robert B. Mueller-Thuns, Joseph T. Rahmeh, Jacob A. Abraham, Jalal A. Wehbeh, Daniel G. Saab
Concurrent Hierarchical and Multilevel Simulation of VLSI Circuits. Simul. 60 (2) (1993)
Shien-Tai Pan, Kimming So, Joseph T. Rahmeh
Improving the Accuracy of Dynamic Branch Prediction Using Branch Correlation. ASPLOS (1992)
Sankaran Karthik, Indira de Souza, Joseph T. Rahmeh, Jacob A. Abraham
Interlock Schemes for Micropiplines: Application to a Self-Timed Rebound Sorter. ICCD (1991)
Daniel G. Saab, Robert B. Mueller-Thuns, David T. Blaauw, Joseph T. Rahmeh, Jacob A. Abraham
Hierarchical multi-level fault simulation of large systems. J. Electron. Test. 1 (2) (1990)
Prithviraj Banerjee, Joseph T. Rahmeh, Craig B. Stunkel, V. S. S. Nair, Kaushik Roy, Vijay Balasubramanian, Jacob A. Abraham
Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor. IEEE Trans. Computers 39 (9) (1990)
Daniel G. Saab, Robert B. Mueller-Thuns, David T. Blaauw, Joseph T. Rahmeh, Jacob A. Abraham
Fault grading of large digital systems. ICCD (1990)
Daniel G. Saab, Ibrahim N. Hajj, Joseph T. Rahmeh
Parallel-concurrent fault simulation. ICCD (1989)
David T. Blaauw, Daniel G. Saab, Robert B. Mueller-Thuns, Jacob A. Abraham, Joseph T. Rahmeh
Automatic Generation of Behavioral Models from Switch-Level Descriptions. DAC (1989)
Prithviraj Banerjee, Joseph T. Rahmeh, Craig B. Stunkel, V. S. S. Nair, Kaushik Roy, Jacob A. Abraham
An evaluation of system-level fault tolerance on the Intel hypercube multiprocessor. FTCS (1988)
Daniel G. Saab, Robert B. Mueller-Thuns, David T. Blaauw, Jacob A. Abraham, Joseph T. Rahmeh
CHAMP: concurrent hierarchical and multilevel program for simulation of VLSI circuits. ICCAD (1988)
Hsi-Ching Shih, Joseph T. Rahmeh, Jacob A. Abraham
FAUST: An MOS Fault Simulator with Timing Information. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5 (4) (1986)
Peter Y.-T. Hsu, Joseph T. Rahmeh, Edward S. Davidson, Jacob A. Abraham
TIDBITS: Speedup Via Time-Delay Bit-Slicing in ALU Design for VLSI Technology. ISCA (1985)