Ibrahim N. Hajj

Publication Activity (10 Years)

Years Active: 1987-2017
Publications (10 Years): 1

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

ISCAS

Publications

Ibrahim N. Hajj
Beyond SPICE. ISCAS (2017)
Ibrahim N. Hajj
On Device Modeling for Circuit Simulation With Application to Carbon-Nanotube and Graphene Nano-Ribbon Field-Effect Transistors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (3) (2015)
Ibrahim N. Hajj
Extended Nodal Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (1) (2012)
Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
Postroute gate sizing for crosstalk noise reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (12) (2004)
Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
Post-Route Gate Sizing for Crosstalk Noise Reduction. ISQED (2003)
Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
Post-route gate sizing for crosstalk noise reduction. DAC (2003)
Murat R. Becer, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj
Early probabilistic noise estimation for capacitively coupled interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (3) (2003)
Murat R. Becer, Rajendran Panda, David T. Blaauw, Ibrahim N. Hajj
Pre-route Noise Estimation in Deep Submicron Integrated Circuits. ISQED (2002)
Geng Bai, Ibrahim N. Hajj
Simultaneous Switching Noise and Resonance Analysis of On-Chip Power Distribution Network. ISQED (2002)
Sumant Ramprasad, Ibrahim N. Hajj, Farid N. Najm
A technique for Improving dual-output domino logic. IEEE Trans. Very Large Scale Integr. Syst. 10 (4) (2002)
Vikram Saxena, Farid N. Najm, Ibrahim N. Hajj
Estimation of state line statistics in sequential circuits. ACM Trans. Design Autom. Electr. Syst. 7 (3) (2002)
Murat R. Becer, David T. Blaauw, Ibrahim N. Hajj, Rajendran Panda
Early probabilistic noise estimation for capacitively coupled interconnects. SLIP (2002)
Murat R. Becer, Vladimir Zolotov, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj
Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model . DATE (2002)
Murat R. Becer, David T. Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov, Jingyan Zuo, Rafi Levy, Ibrahim N. Hajj
A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance. ISQED (2001)
Ninglong Lu, Ibrahim N. Hajj
A Fast Coupling Aware Delay Estimation Scheme Based on Simplified Circuit Model. ISQED (2001)
Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj
Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI Circuits. DAC (2001)
Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj
Maximum power supply noise estimation in VLSI circuits using multimodal genetic algorithms. ICECS (2001)
Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj
RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits. ISQED (2001)
Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj
RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits. ISQED (2001)
Sudhakar Bobba, Ibrahim N. Hajj
Input vector generation for maximum intrinsic decoupling capacitance of VLSI circuits. ISCAS (5) (2001)
Sudhakar Bobba, Ibrahim N. Hajj
Maximum voltage variation in the power distribution network of VLSI circuits with RLC models. ISLPED (2001)
Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos, G. Stamoulis
Architectural and compiler techniques for energy reduction in high-performance microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 8 (3) (2000)
Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos
Using dynamic cache management techniques to reduce energy in general purpose processors. IEEE Trans. Very Large Scale Integr. Syst. 8 (6) (2000)
Ninglong Lu, Ibrahim N. Hajj
A hierarchical based approach for coupling aware delay analysis of combinational logic blocks. ICECS (2000)
Sudhakar Bobba, Ibrahim N. Hajj
Peak current estimation for digital filters. ICASSP (2000)
Mohammad M. Mansour, Makram M. Mansour, Ibrahim N. Hajj, Naresh R. Shanbhag
Instruction scheduling for low power on dynamically variable voltage processors. ICECS (2000)
Sudhakar Bobba, Ibrahim N. Hajj
Current-Mode Threshold Logic Gates. ICCD (2000)
Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj
Simulation and Optimization of the Power Distribution Network in VLSI Circuits. ICCAD (2000)
Sudhakar Bobba, Ibrahim N. Hajj
High-performance bidirectional repeaters. ACM Great Lakes Symposium on VLSI (2000)
Murat R. Becer, Ibrahim N. Hajj
An Analytical Model for Delay and Crosstalk Estimation with Application to Decoupling. ISQED (2000)
Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj
Power Bus Maximum Voltage Drop in Digital VLSI Circuits. ISQED (2000)
Murat R. Becer, Ibrahim N. Hajj
An analytical model for delay and crosstalk estimation in interconnects under general switching conditions. ICECS (2000)
Andreas G. Veneris, Ibrahim N. Hajj
Design error diagnosis and correction via test vector simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (12) (1999)
Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
A coding framework for low-power address and data busses. IEEE Trans. Very Large Scale Integr. Syst. 7 (2) (1999)
Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
Low-power distributed arithmetic architectures using nonuniform memory partitioning. ISCAS (3) (1999)
Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos
An analytical, transistor-level energy model for SRAM-based caches. ISCAS (6) (1999)
Ninglong Lu, Ibrahim N. Hajj
An Exact Analytical Time-Domain Model Of Distributed RC Interconnects for High Speed Nonlinear Circuit Applications. Great Lakes Symposium on VLSI (1999)
Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos, George D. Stamoulis
Energy and Performance Improvements in Microprocessor Design Using a Loop Cache. ICCD (1999)
Andreas G. Veneris, Ibrahim N. Hajj
Correcting multiple design errors in digital VLSI circuits. ISCAS (1) (1999)
Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
Information-theoretic bounds on average signal transition activity [VLSI systems]. IEEE Trans. Very Large Scale Integr. Syst. 7 (3) (1999)
Sumant Ramprasad, Ibrahim N. Hajj, Farid N. Najm
An optimization technique for dual-output domino logic. ISLPED (1999)
Andreas G. Veneris, Ibrahim N. Hajj, Srikanth Venkataraman, W. Kent Fuchs
Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits. VTS (1999)
Ninglong Lu, Ibrahim N. Hajj
A reduced-order scheme for coupled lumped-distributed interconnect simulation. ISCAS (6) (1999)
Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos
Using dynamic cache management techniques to reduce energy in a high-performance processor. ISLPED (1999)
Sudhakar Bobba, Ibrahim N. Hajj, Naresh R. Shanbhag
Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures. VLSI Design (1999)
Andreas G. Veneris, Ibrahim N. Hajj
A hybrid approach to design error detection and correction [VLSI digital circuits]. ICECS (1999)
Sudhakar Bobba, Ibrahim N. Hajj
Estimation of maximum current envelope for power bus analysis and design. ISPD (1998)
Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
Decorrelating (DECOR) transformations for low-power adaptive filters. ISLPED (1998)
Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
Coding for Low-Power Address and Data Busses: A Source-Coding Framework and Applications. VLSI Design (1998)
Sudhakar Bobba, Ibrahim N. Hajj
Maximum Current Estimation in Programmable Logic Arrays. Great Lakes Symposium on VLSI (1998)
Nikolaos Bellas, Ibrahim N. Hajj, George D. Stamoulis, Constantine D. Polychronopoulos
Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors. ISLPED (1998)
Vikram Saxena, Farid N. Najm, Ibrahim N. Hajj
Monte-Carlo approach for power estimation in sequential circuits. ED&TC (1997)
Tzuhao Chen, Ibrahim N. Hajj
GOLDENGATE: a fast and accurate bridging fault simulator under a hybrid logic/IDDQ testing environment. ICCAD (1997)
Pi-Yu Chung, Ibrahim N. Hajj
Diagnosis and correction of multiple logic design errors in digital circuits. IEEE Trans. Very Large Scale Integr. Syst. 5 (2) (1997)
Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
Analytical Estimation of Transition Activity From Word-Level Signal Statistics. DAC (1997)
Andreas G. Veneris, Ibrahim N. Hajj
A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits. Great Lakes Symposium on VLSI (1997)
Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
Analytical estimation of signal transition activity from word-level statistics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (7) (1997)
Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
Achievable bounds on signal transition activity. ICCAD (1997)
Ping-Chung Li, Ibrahim N. Hajj
Computer-aided redesign of VLSI circuits for hot-carrier reliability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (5) (1996)
Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel
Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits. VTS (1996)
Terry Lee, Weitong Chuang, Ibrahim N. Hajj, W. Kent Fuchs
Circuit-level dictionaries of CMOS bridging faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (5) (1995)
Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj
Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (8) (1995)
Farid N. Najm, Shashank Goel, Ibrahim N. Hajj
Power Estimation in Sequential Circuits. DAC (1995)
Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj
Timing and area optimization for standard-cell VLSI circuit design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (3) (1995)
Terry Lee, Weitong Chuang, Ibrahim N. Hajj, W. Kent Fuchs
Circuit-level dictionaries of CMOS bridging faults. VTS (1994)
Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj
Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits. ISCAS (1994)
Ping-Chung Li, Georgios I. Stamoulis, Ibrahim N. Hajj
A probabilistic timing approach to hot-carrier effect estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (10) (1994)
Pi-Yu Chung, Yi-Min Wang, Ibrahim N. Hajj
Logic design error diagnosis and correction. IEEE Trans. Very Large Scale Integr. Syst. 2 (3) (1994)
Weitong Chuang, Ibrahim N. Hajj
Delay and area optimization for compact placement by gate resizing and relocation. ICCAD (1994)
Andrew T. Yang, Yu-Hsu Chang, Daniel G. Saab, Ibrahim N. Hajj
Switch-level timing simulation of bipolar ECL circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (4) (1993)
Pi-Yu Chung, Yi-Min Wang, Ibrahim N. Hajj
Diagnosis and Correction of Logic Design Errors in Digital Circuits. DAC (1993)
Harish Kriplani, Farid N. Najm, Ping Yang, Ibrahim N. Hajj
Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits. DAC (1993)
Weitong Chuang, Ibrahim N. Hajj
Fast Mixed-Mode Simulation for Accurate MOS Bridging Fault Detection. ISCAS (1993)
Georgios I. Stamoulis, Ibrahim N. Hajj
Improved Techniques for Probabilistic Simulation Including Signal Correlation Effects. DAC (1993)
Ping-Chung Li, Ibrahim N. Hajj
Computer-Aided Redesign of VLSI Circuits for Hot-Carrier Reliability. ICCD (1993)
Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj
A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area. ICCAD (1993)
Pi-Yu Chung, Ibrahim N. Hajj, Janak H. Patel
Efficient Variable Ordering Heuristics for Shared ROBDD. ISCAS (1993)
Ibrahim N. Hajj, Terry Lee
Simulation of physical faults in VLSI circuits. VTS (1992)
Pi-Yu Chung, Ibrahim N. Hajj
ACCORD: Automatic Catching and CORrection of Logic Design Errors in Combinatorial Circuits. ITC (1992)
Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj
Maximum Current Estimation in CMOS Circuits. DAC (1992)
Ping-Chung Li, Georgios I. Stamoulis, Ibrahim N. Hajj
A probabilistic timing approach to hot-carrier effect estimation. ICCAD (1992)
Farid N. Najm, Ibrahim N. Hajj, Ping Yang
An extension of probabilistic simulation for reliability analysis of CMOS VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 (11) (1991)
Terry Lee, Ibrahim N. Hajj
A Switch-Level Matrix Approach to Transistor-Level Fault Simulation. ICCAD (1991)
Ibrahim N. Hajj, Stig Skelboe
A multilevel parallel solver for block tridiagonal and banded linear systems. Parallel Comput. 15 (1-3) (1990)
Young-Hyun Jun, Ibrahim N. Hajj, Sang-Heon Lee, Song-Bai Park
High speed VLSI logic simulation using bitwise operations and parallel processing. ICCD (1990)
P. Gee, Min-You Wu, S. M. Kang, Ibrahim N. Hajj
A metal - metal matrix cell generator for multi-level metal MOS technology. Integr. 9 (1) (1990)
Ibrahim N. Hajj
An Algebra for Switch-Level Simulation. ICCAD (1990)
Farid N. Najm, Richard Burch, Ping Yang, Ibrahim N. Hajj
Probabilistic simulation for reliability analysis of CMOS VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 (4) (1990)
Farid N. Najm, Ibrahim N. Hajj
The complexity of fault detection in MOS VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 (9) (1990)
David Overhauser, Ibrahim N. Hajj, Yi-Fan Hsu
Automatic mixed-mode timing simulation. ICCAD (1989)
P. Gee, Ibrahim N. Hajj, Sung-Mo Kang
A custom cell generation system for double-metal CMOS technology. ICCAD (1989)
Farid N. Najm, Ibrahim N. Hajj, Ping Yang
Electromigration median time-to-failure based on a stochastic current waveform. ICCD (1989)
Daniel G. Saab, Ibrahim N. Hajj, Joseph T. Rahmeh
Parallel-concurrent fault simulation. ICCD (1989)
Min-You Wu, Ibrahim N. Hajj
Switching network logic approach to sequential MOS circuit design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (7) (1989)
Farid N. Najm, Ibrahim N. Hajj, Ping Yang
Computation of bus current variance for reliability estimation of VLSI circuits. ICCAD (1989)
David Overhauser, Ibrahim N. Hajj
A tabular macromodeling approach to fast timing simulation including parasitics. ICCAD (1988)
Mi-Chang Chang, Ibrahim N. Hajj
iPRIDE: a parallel integrated circuit simulator using direct method. ICCAD (1988)
Daniel G. Saab, Andrew T. Yang, Ibrahim N. Hajj
Delay Modeling and Time of Bipolar Digital Circuits. DAC (1988)
Farid N. Najm, Richard Burch, Ping Yang, Ibrahim N. Hajj
CREST-a current estimator for CMOS circuits. ICCAD (1988)
Tat-Kwan Yu, Sung-Mo Kang, Ibrahim N. Hajj, Timothy N. Trick
iEDISON: an interactive statistical design tool for MOS VLSI circuits. ICCAD (1988)

Ibrahim N. Hajj.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Ibrahim N. Hajj