A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area.
Weitong ChuangSachin S. SapatnekarIbrahim N. HajjPublished in: ICCAD (1993)
Keyphrases
- optimization algorithm
- learning algorithm
- objective function
- preprocessing
- computational cost
- k means
- cost function
- worst case
- high accuracy
- convergence rate
- combinatorial optimization
- theoretical analysis
- computational complexity
- np hard
- dynamic programming
- experimental evaluation
- improved algorithm
- optimization method
- detection algorithm
- expectation maximization
- linear programming
- high speed
- optimization problems
- power consumption
- times faster
- neural network
- similarity measure
- probabilistic model
- stochastic gradient