Low-power distributed arithmetic architectures using nonuniform memory partitioning.
Sumant RamprasadNaresh R. ShanbhagIbrahim N. HajjPublished in: ISCAS (3) (1999)
Keyphrases
- low power
- power consumption
- low cost
- high speed
- single chip
- distributed systems
- wireless transmission
- power dissipation
- low power consumption
- vlsi circuits
- peer to peer
- high power
- power reduction
- vlsi architecture
- digital signal processing
- nm technology
- logic circuits
- image processing
- delay insensitive
- real time
- multi channel