Andrew R. Pleszkun

Publication Activity (10 Years)

Years Active: 1983-2003
Publications (10 Years): 0

Publications

Stephen Aiken, Dirk Grunwald, Andrew R. Pleszkun, Jesse Willek
A Performance Analysis of the iSCSI Protocol. IEEE Symposium on Mass Storage Systems (2003)
James E. Smith, Andrew R. Pleszkun
Implementation of Precise Interupts in Pipelined Processors. 25 Years ISCA: Retrospectives and Reprints (1998)
Dirk Grunwald, Artur Klauser, Srilatha Manne, Andrew R. Pleszkun
Confidence Estimation for Speculation Control. ISCA (1998)
Gary S. Tyson, Matthew K. Farrens, John Matthews, Andrew R. Pleszkun
Managing data caches using selective cache line replacement. Int. J. Parallel Program. 25 (3) (1997)
Gary S. Tyson, Matthew K. Farrens, John Matthews, Andrew R. Pleszkun
A modified approach to data cache management. MICRO (1995)
Matthew K. Farrens, Gary S. Tyson, Andrew R. Pleszkun
A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors. ISCA (1994)
Andrew R. Pleszkun
Techniques for compressing program address traces. MICRO (1994)
Gary S. Tyson, Matthew K. Farrens, Andrew R. Pleszkun
MISC: a Multiple Instruction Stream Computer. MICRO (1992)
Matthew K. Farrens, Andrew R. Pleszkun
Implementation of the PIPE Processor. Computer 24 (1) (1991)
Matthew K. Farrens, Andrew R. Pleszkun
Strategies for Achieving Improved Processor Throughput. ISCA (1991)
Matthew K. Farrens, Andrew R. Pleszkun
An evaluation of functional unit lengths for single-chip processors. MICRO (1990)
Matthew K. Farrens, Andrew R. Pleszkun
Improving Performance of Small On-Chip Instruction Caches. ISCA (1989)
Andrew R. Pleszkun, Gurindar S. Sohi
Multiple instruction issue and single-chip processors. MICRO (1988)
James E. Smith, Andrew R. Pleszkun
Implementing Precise Interrupts in Pipelined Processors. IEEE Trans. Computers 37 (5) (1988)
Andrew R. Pleszkun, Gurindar S. Sohi
The Performance Potential of Multiple Functional Unit Processors. ISCA (1988)
Andrew R. Pleszkun, Matthew Thazhuthaveetil
The Architecture of Lisp Machines. Computer 20 (3) (1987)
Andrew R. Pleszkun, James R. Goodman, Wei-Chung Hsu, R. T. Joersz, George E. Bier, Philip J. Woest, P. B. Schechter
WISQ: A Restartable Architecture Using Queues. ISCA (1987)
Matthew Thazhuthaveetil, Andrew R. Pleszkun
On the Structural Locality of Reference in LISP List Access Streams. Inf. Process. Lett. 26 (2) (1987)
Andrew R. Pleszkun, Gurindar S. Sohi, Bassam Z. Kahhaleh, Edward S. Davidson
Features of the Structured Memory Access (SMA) Architecture. COMPCON (1986)
Andrew R. Pleszkun, Matthew Thazhuthaveetil
An Architecture for Efficient Lisp List Access. ISCA (1986)
James R. Goodman, Jian-tu Hsieh, Koujuch Liou, Andrew R. Pleszkun, P. B. Schechter, Honesty C. Young
PIPE: A VLSI Decoupled Architecture. ISCA (1985)
James E. Smith, Andrew R. Pleszkun
Implementation of Precise Interrupts in Pipelined Processors. ISCA (1985)
George E. Bier, Andrew R. Pleszkun
An algorithm for design rule checking on a multiprocessor. DAC (1985)
Andrew R. Pleszkun, Edward S. Davidson
Structured Memory Access Architecture. ICPP (1983)