Scheduling instruction effects for a statically pipelined processor.
B. DavisRyan BairdPeter GavinMagnus SjälanderIan FinlaysonF. RasapourG. CookGang-Ryung UhDavid B. WhalleyGary S. TysonPublished in: CASES (2015)
Keyphrases
- instruction set
- computer based instruction
- parallel processors
- multiprocessor systems
- computer architecture
- scheduling problem
- scheduling algorithm
- data flow
- flexible manufacturing systems
- parallel architecture
- instruction set architecture
- memory hierarchy
- round robin
- parallel processing
- cooperative learning
- student achievement
- level parallelism
- multimedia
- resource constraints
- application specific
- learning strategies