Improving Low Power Processor Efficiency with Static Pipelining.
Ian FinlaysonGang-Ryung UhDavid B. WhalleyGary S. TysonPublished in: Interaction between Compilers and Computer Architectures (2011)
Keyphrases
- low power
- high speed
- single chip
- power consumption
- gate array
- low cost
- high power
- parallel processing
- digital signal processing
- logic circuits
- vlsi architecture
- low power consumption
- wireless transmission
- cmos technology
- mixed signal
- vlsi circuits
- power reduction
- delay insensitive
- highly efficient
- image sensor
- operating system
- real time