Double Throughput Multiply-Accumulate unit for FlexCore processor enhancements.

Tung Thanh Hoang Magnus Själander Per Larsson-Edefors

Published in: IPDPS (2009)

Keyphrases

response time
high speed
floating point
processing units
instruction set
parallel processing
resource utilization
low latency
single chip
higher throughput
web services
steady state
fixed point
computer architecture
parallel processors
loss probability