Tung Thanh Hoang

Publication Activity (10 Years)

Years Active: 2009-2022
Publications (10 Years): 3

Top Topics

Data Processing

Foreseeable Future

Energy Efficiency

Top Venues

Publications

Wen Ma, Tung Thanh Hoang, Brian Hoskins, Matthew W. Daniels, Jabez J. McClelland, Yutong Gao, Gina C. Adam, Martin Lueker-Boden
Effect of OTS Selector Reliabilities on NVM Crossbar-based Neuromorphic Training. IRPS (2022)
Won Ho Choi, Pi-Feng Chiu, Wen Ma, Gertjan Hemink, Tung Thanh Hoang, Martin Lueker-Boden, Zvonimir Bandic
An In-Flash Binary Neural Network Accelerator with SLC NAND Flash Array. ISCAS (2020)
Tung Thanh Hoang, Amirali Shambayati, Andrew A. Chien
A Data Layout Transformation (DLT) accelerator: Architectural support for data movement optimization in accelerated-centric heterogeneous systems. DATE (2016)
Andrew A. Chien, Tung Thanh Hoang, Dilip P. Vasudevan, Yuanwei Fang, Amirali Shambayati
10x10: A Case Study in Highly-Programmable and Energy-Efficient Heterogeneous Federated Architecture. SIGARCH Comput. Archit. News 43 (2) (2015)
Yuanwei Fang, Tung Thanh Hoang, Michela Becchi, Andrew A. Chien
Fast support for unstructured data processing: the unified automata processor. MICRO (2015)
Tung Thanh Hoang, Amirali Shambayati, Henry Hoffmann, Andrew A. Chien
Does arithmetic logic dominate data movement? a systematic comparison of energy-efficiency for FFT accelerators. ASAP (2015)
Tung Thanh Hoang, Amirali Shambayati, Calvin Deutschbein, Henry Hoffmann, Andrew A. Chien
Performance and energy limits of a processor-integrated FFT accelerator. HPEC (2014)
Muhammad Waqar Azhar, Magnus Själander, Hasan Ali, Akshay Vijayashekar, Tung Thanh Hoang, Kashan Khurshid Ansari, Per Larsson-Edefors
Viterbi Accelerator for Embedded Processor Datapaths. ASAP (2012)
Tung Thanh Hoang, Per Larsson-Edefors
Data-Width-Driven Power Gating of Integer Arithmetic Circuits. ISVLSI (2012)
Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors
A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2010)
Muhammad Waqar Azhar, Tung Thanh Hoang, Per Larsson-Edefors
Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor. DSD (2010)
Tung Thanh Hoang, Ulf Jalmbrant, Erik der Hagopian, Kasyab P. Subramaniyan, Magnus Själander, Per Larsson-Edefors
Design space exploration for an embedded processor with flexible datapath interconnect. ASAP (2010)
Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors
High-speed, energy-efficient 2-cycle Multiply-Accumulate architecture. SoCC (2009)
Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors
Double Throughput Multiply-Accumulate unit for FlexCore processor enhancements. IPDPS (2009)