Dilip P. Vasudevan

Publication Activity (10 Years)

Years Active: 2004-2020
Publications (10 Years): 5

Top Topics

Machine Learning

Classical Logic

Enabling Technology

Top Venues

IEEE Trans. Biomed. Circuits Syst.

Publications

Weilong Cui, Georgios Tzimpragos, Yu Tao, Joseph McMahan, Deeksha Dangwal, Nestan Tsiskaridze, George Michelogiannakis, Dilip P. Vasudevan, Timothy Sherwood
Language Support for Navigating Architecture Design in Closed Form. ACM J. Emerg. Technol. Comput. Syst. 16 (1) (2020)
Dilip P. Vasudevan, George Michelogiannakis, David Donofrio, John Shalf
PARADISE - Post-Moore Architecture and Accelerator Design Space Exploration Using Device Level Simulation and Experiments. ISPASS (2019)
Sebastian Werner, Pouya Fotouhi, Xian Xiao, Marjan Fariborz, S. J. Ben Yoo, George Michelogiannakis, Dilip P. Vasudevan
3D photonics as enabling technology for deep 3D DRAM stacking. MEMSYS (2019)
Dilip P. Vasudevan, George Michelogiannakis, David Donofrio, John Shalf
CASPER - Configurable design space exploration of programmable architectures for machine learning using beyond moore devices. NANOARCH (2017)
Dilip P. Vasudevan, Anastasiia Butko, George Michelogiannakis, David Donofrio, John Shalf
Towards an Integrated Strategy to Preserve Digital Computing Performance Scaling Using Emerging Technologies. ISC Workshops (2017)
Dilip P. Vasudevan, Andrew A. Chien
The Bit-Nibble-Byte MicroEngine (BnB) for Efficient Computing on Short Data. ACM Great Lakes Symposium on VLSI (2015)
Andrew A. Chien, Tung Thanh Hoang, Dilip P. Vasudevan, Yuanwei Fang, Amirali Shambayati
10x10: A Case Study in Highly-Programmable and Energy-Efficient Heterogeneous Federated Architecture. SIGARCH Comput. Archit. News 43 (2) (2015)
Abhishek Roy, Alicia Klinefelter, Farah B. Yahya, Xing Chen, Luisa Patricia Gonzalez-Guerrero, Christopher J. Lukas, Divya Akella Kamakshi, James Boley, Kyle Craig, Muhammad Faisal, Seunghyun Oh, Nathan E. Roberts, Yousef Shakhsheer, Aatmesh Shrivastava, Dilip P. Vasudevan, David D. Wentzloff, Benton H. Calhoun
A 6.45 μW Self-Powered SoC With Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios for Portable Biomedical Systems. IEEE Trans. Biomed. Circuits Syst. 9 (6) (2015)
Jiaoyan Chen, Dilip P. Vasudevan, Michel P. Schellekens, Emanuel M. Popovici
Ultra Low Power Asynchronous Charge Sharing Logic. J. Low Power Electron. 8 (4) (2012)
Jiaoyan Chen, Emanuel M. Popovici, Dilip P. Vasudevan, Michel P. Schellekens
Ultra Low Power Booth Multiplier Using Asynchronous Logic. ASYNC (2012)
Xiaodong Wang, Dilip P. Vasudevan, Hsien-Hsin S. Lee
Global Built-In Self-Repair for 3D memories with redundancy sharing and parallel testing. 3DIC (2011)
Jiaoyan Chen, Dilip P. Vasudevan, Emanuel M. Popovici, Michel P. Schellekens
Design of a Low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit Using a Bidirectional Adder. DSD (2011)
Tingcong Ye, Dilip P. Vasudevan, Jiaoyan Chen, Emanuel M. Popovici, Michel P. Schellekens
Static Average Case Power Estimation Technique for Block Ciphers. DSD (2010)
Jiaoyan Chen, Dilip P. Vasudevan, Emanuel M. Popovici, Michel P. Schellekens
Reversible online BIST using bidirectional BILBO. Conf. Computing Frontiers (2010)
Jiaoyan Chen, Dilip P. Vasudevan, Emanuel M. Popovici, Michel P. Schellekens, Peter Gillen
Design and analysis of a novel 8T SRAM cell for adiabatic and non-adiabatic operations. ICECS (2010)
Dilip P. Vasudevan, Aristides Efthymiou
A Partial Scan Based Test Generation for Asynchronous Circuits. DDECS (2008)
Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson
Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2007)
Jia Di, Dilip P. Vasudevan
Synthesis of Nanoelectronic Circuits on Delay-Insensitive Cellular Arrays. DELTA (2006)
Dilip P. Vasudevan, Parag K. Lala, Jia Di, James Patrick Parkerson
Reversible-logic design with online testability. IEEE Trans. Instrum. Meas. 55 (2) (2006)
Dilip P. Vasudevan, Parag K. Lala
A Technique for Modular Design of Self-Checking Carry-Select Adder. DFT (2005)
Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson
CMOS Realization of Online Testable Reversible Logic Gates. ISVLSI (2005)
Jia Di, Parag K. Lala, Dilip P. Vasudevan
On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits. DFT (2005)
Dilip P. Vasudevan, Parag K. Lala
A New Reversible Logic Gate and its Applications. ESA/VLSI (2004)
Dilip P. Vasudevan, James Patrick Parkerson, Parag K. Lala
Logic implementation using a reversible gate. Circuits, Signals, and Systems (2004)
Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson
A Novel Approach for On-line Testable Reversible Logic Circuit Desig. Asian Test Symposium (2004)
Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson
Online Testable Reversible Logic Circuit Design using NAND Blocks. DFT (2004)