Parag K. Lala

Publication Activity (10 Years)

Years Active: 1981-2010
Publications (10 Years): 0

Publications

Parag K. Lala
A Quantum Key Distribution Protocol. Security and Management (2010)
Parag K. Lala, Adam Mathews, James Patrick Parkerson
An Approach for Implementing State Machines with Online Testability. VLSI Design 2010 (2010)
Parag K. Lala
On FPGA Design with Self-checking and Fault Tolerance Capability. ERSA (2008)
Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson
Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2007)
Jia Di, Parag K. Lala
Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems. J. Electron. Test. 23 (2-3) (2007)
Dilip P. Vasudevan, Parag K. Lala, Jia Di, James Patrick Parkerson
Reversible-logic design with online testability. IEEE Trans. Instrum. Meas. 55 (2) (2006)
Parag K. Lala, B. Kiran Kumar, James Patrick Parkerson
On self-healing digital system design. Microelectron. J. 37 (4) (2006)
Dilip P. Vasudevan, Parag K. Lala
A Technique for Modular Design of Self-Checking Carry-Select Adder. DFT (2005)
Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson
CMOS Realization of Online Testable Reversible Logic Gates. ISVLSI (2005)
C. K. Tang, Parag K. Lala, James Patrick Parkerson
A Technique for Designing Totally Self-Checking Domino Logic Circuits. ISQED (2005)
Jia Di, Parag K. Lala, Dilip P. Vasudevan
On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits. DFT (2005)
Dilip P. Vasudevan, Parag K. Lala
A New Reversible Logic Gate and its Applications. ESA/VLSI (2004)
Dilip P. Vasudevan, James Patrick Parkerson, Parag K. Lala
Logic implementation using a reversible gate. Circuits, Signals, and Systems (2004)
Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson
A Novel Approach for On-line Testable Reversible Logic Circuit Desig. Asian Test Symposium (2004)
Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson
Online Testable Reversible Logic Circuit Design using NAND Blocks. DFT (2004)
B. Kiran Kumar, Parag K. Lala
On-line Detection of Faults in Carry-Select Adders. ITC (2003)
Parag K. Lala, B. Kiran Kumar
An Architecture for Self-Healing Digital Systems. J. Electron. Test. 19 (5) (2003)
Parag K. Lala
A Single Error Correcting and Double Error Detecting Coding Scheme for Computer Memory Systems. DFT (2003)
S. R. Seward, Parag K. Lala
Fault Injection for Verifying Testability at the VHDL Level. ITC (2003)
Parag K. Lala, B. Kiran Kumar
An FPGA architecture with built-in error correction capability. FPGA (2003)
S. R. Seward, Parag K. Lala
Fault Injection in Digital Logic Circuits at the VHDL Level. IOLTS (2003)
Parag K. Lala, Alfred L. Burress
Self-checking logic design for FPGA implementation. IEEE Trans. Instrum. Meas. 52 (5) (2003)
Whitney J. Townsend, Jacob A. Abraham, Parag K. Lala
On-Line Error Detecting Constant Delay Adder. IOLTS (2003)
Parag K. Lala, B. Kiran Kumar
An Architecture for Self-Healing Digital Systems. IOLTW (2002)
Parag K. Lala, K. K. Bondali
On Biologically-Inspired Design of Fault-Tolerant Digital Systems. DELTA (2002)
Parag K. Lala, B. Kiran Kumar
Human Immune System Inspired Architecture for Self-Healing Digital Systems. ISQED (2002)
Whitney J. Townsend, Mitchell A. Thornton, Parag K. Lala
On-line Error Detection in a Carry-free Adder. IWLS (2002)
Parag K. Lala, Mark G. Karpovsky
An Approach for Designing On-Line Testable State Machines. IOLTW (2001)
Parag K. Lala, Alvernon Walker
A Unified Scheme for Designing Testable State Machines. Asian Test Symposium (2001)
Parag K. Lala, Alvernon Walker
A Fine Grain Configurable Logic Block for Self-checking FPGAs. VLSI Design 2001 (4) (2001)
Parag K. Lala, Alvernon Walker
On-Line Error Detectable Carry-Free Adder Design. DFT (2001)
Parag K. Lala, Alvernon Walker
An On-Line Reconfigurable FPGA Architecture. DFT (2000)
Alvernon Walker, Parag K. Lala
A Transition Based BIST Approach for Passive Analog Circuits. ISQED (2000)
Parag K. Lala
Guest Editorial. VLSI Design 2000 (1) (2000)
Jong O. Kim, Parag K. Lala, Young Gun Kim, Heung-Soo Kim
Fault Analysis of the Multiple Valued Logic Using Spectral Method. ISMVL (2000)
Parag K. Lala, Anup Singh, Alvernon Walker
A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAs. DFT (1999)
Parag K. Lala, Alfred L. Burress
A technique for designing self-checking logic for FPGAs. ISCAS (1) (1999)
Parag K. Lala, Alfred L. Burress
Self-Checking Logic Design for LUT-Based FPGAs. FPGA (1999)
Parag K. Lala
Guest Editorial. VLSI Design 1998 (4) (1998)
Fadi Busaba, Parag K. Lala, Alvernon Walker
On Self-Checking Design of CMOS Circuits for Multiple Faults. VLSI Design 1998 (2) (1998)
Alvernon Walker, Algernon P. Henry, Parag K. Lala
An approach for detecting bridging faults in CMOS domino logic circuits using dynamic power supply current monitoring. DFT (1997)
Alfred L. Burress, Parag K. Lala
On-Line Testable Logic Desgin for FPGA Implementation. ITC (1997)
Parag K. Lala, S. Yang, Fadi Busaba
A unified approach for off-line and on-line testing of VLSI systems. DFT (1996)
K. Lai, Parag K. Lala
Multiple Fault Detection in Fan-Out Free Circuits Using Minimal Single Fault Test Set. IEEE Trans. Computers 45 (6) (1996)
D. A. Pierce, Parag K. Lala
Modular implementation of efficient self-checking checkers for the Berger code. J. Electron. Test. 9 (3) (1996)
Fadi Y. Busaba, Parag K. Lala
A graph coloring based approach for self-checking logic circuit design. Asian Test Symposium (1995)
Fadi Y. Busaba, Parag K. Lala
Self-checking combinational circuit design for single and unidirectional multibit error. J. Electron. Test. 5 (1) (1994)
Fadi Busaba, Parag K. Lala
Techniques for Self-Checking Combinational Logic Synthesis. VLSI Design 2 (3) (1994)
J. Q. Wang, Parag K. Lala
Partially Strongly Fault Secure and Partially Strongly Code Disjoint I-out-of-3 Code Checker. IEEE Trans. Computers 43 (10) (1994)
Fadi Busaba, Parag K. Lala
An Approach for Self-Checking Realization of Interacting Finite State Machines. VLSI Design 1 (4) (1994)
Fadi Y. Busaba, Parag K. Lala
Input and output encoding techniques for on-line error detection in combinational logic circuits. VTS (1993)
B. Kolla, Parag K. Lala, K. C. Yarlagadda
A concurrent checking scheme for single and multibit errors in logic circuits. VTS (1992)
Alvernon Walker, Winser E. Alexander, Parag K. Lala
Fault Diagnosis in Analog Circuits Using Element Modulation. IEEE Des. Test Comput. 9 (1) (1992)
Manjit S. Cheema, Parag K. Lala
A new technique for totally self-checking CMOS circuit design for stuck-on and stuck-off faults. VTS (1992)
D. L. Tao, Carlos R. P. Hartmann, Parag K. Lala
A General Technique for Designing Totally Self-Checking Checker for 1-out-of-N Code with Minimum Gate Delay. IEEE Trans. Computers 41 (7) (1992)
D. L. Tao, Carlos R. P. Hartmann, Parag K. Lala
A Note on t-EC/d-UED Codes. IEEE Trans. Computers 40 (5) (1991)
Parag K. Lala, Fadi Y. Busaba, K. C. Yarlagadda
An approach for designing self-checking logic using residue codes. VTS (1991)
D. L. Tao, Carlos R. P. Hartmann, Parag K. Lala
An efficient class of unidirectional error detecting/correcting codes. IEEE Trans. Computers 37 (6) (1988)
D. L. Tao, Carlos R. P. Hartmann, Parag K. Lala
A Concurrent Testing Strategy for PLAs. ITC (1986)
Parag K. Lala
On Built-In Testing of VLSI Chips. ITC (1986)
Parag K. Lala
Testing using a minimal number of instructions. Microprocess. Microsystems 5 (7) (1981)