CMOS Realization of Online Testable Reversible Logic Gates.

Dilip P. Vasudevan Parag K. Lala James Patrick Parkerson

Published in: ISVLSI (2005)

Keyphrases

delay insensitive
online learning
logic circuits
low power
real time
high speed
low cost
cellular automata
random access memory
markov chain
predicate logic
data sets
genetic algorithm
modal logic
website
defeasible logic