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High-speed and low-power multipliers using the Baugh-Wooley algorithm and HPM reduction tree.

Magnus SjälanderPer Larsson-Edefors
Published in: ICECS (2008)
Keyphrases
  • low power
  • high speed
  • low cost
  • tree structure
  • vlsi architecture
  • real time
  • super resolution
  • power consumption
  • single pass
  • digital signal processing
  • high power
  • power reduction
  • deblocking filter
  • signal processor