Per Stenström

ORCID

Publication Activity (10 Years)

Years Active: 1987-2024
Publications (10 Years): 38

Top Venues

ACM Trans. Archit. Code Optim.

IPDPS

CoRR

ICPP

Publications

Qi Shao, Angelos Arelakis, Per Stenström
HMComp: Extending Near-Memory Capacity using Compression in Hybrid Memory. ICS (2024)
Piyumal Ranawaka, Muhammad Waqar Azhar, Per Stenström
DNNOPT: A Framework for Efficiently Selecting On-chip Memory Loop Optimizations of DNN Accelerators. CF (2024)
Nadja Ramhöj Holtryd, Madhavan Manivannan, Per Stenström
SoK: Analysis of Root Causes and Defense Strategies for Attacks on Microarchitectural Optimizations. EuroS&P (2023)
Lluc Alvarez, Abraham Ruiz, Arnau Bigas-Soldevilla, Pavel Kuroedov, Alberto González, Hamsika Mahale, Noe Bustamante, Albert Aguilera, Francesco Minervini, Javier Salamero, Oscar Palomar, Vassilis Papaefstathiou, Antonis Psathakis, Nikolaos Dimou, Michalis Giaourtas, Iasonas Mastorakis, Georgios Ieronymakis, Georgios-Michail Matzouranis, Vassilis Flouris, Nick Kossifidis, Manolis Marazakis, Bhavishya Goel, Madhavan Manivannan, Ahsen Ejaz, Panagiotis Strikos, Mateo Vázquez, Ioannis Sourdis, Pedro Trancoso, Per Stenström, Jens Hagemeyer, Lennart Tigges, Nils Kucza, Jean-Marc Philippe, Ioannis Papaefstathiou
eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem. CF (2023)
Muhammad Waqar Azhar, Madhavan Manivannan, Per Stenström
Approx-RM: Reducing Energy on Heterogeneous Multicore Processors under Accuracy and Timing Constraints. ACM Trans. Archit. Code Optim. 20 (3) (2023)
Nadja Ramhöj Holtryd, Madhavan Manivannan, Per Stenström
SCALE: Secure and Scalable Cache Partitioning. HOST (2023)
Nadja Ramhöj Holtryd, Madhavan Manivannan, Per Stenström
SoK: Analysis of Root Causes and Defense Strategies for Attacks on Microarchitectural Optimizations. CoRR (2022)
Alexandra Angerd, Angelos Arelakis, Vasilis Spiliopoulos, Erik Sintorn, Per Stenström
GBDI: Going Beyond Base-Delta-Immediate Compression with Global Bases. HPCA (2022)
Muhammad Waqar Azhar, Miquel Pericàs, Per Stenström
Task-RM: A Resource Manager for Energy Reduction in Task-Parallel Applications under Quality of Service Constraints. ACM Trans. Archit. Code Optim. 19 (1) (2022)
Petros Voudouris, Per Stenström, Risat Pathan
Bounding the execution time of parallel applications on unrelated multiprocessors. Real Time Syst. 58 (2) (2022)
Mehrzad Nejat, Madhavan Manivannan, Miquel Pericàs, Per Stenström
Cooperative Slack Management: Saving Energy of Multicore Processors by Trading Performance Slack Between QoS-Constrained Applications. ACM Trans. Archit. Code Optim. 19 (2) (2022)
Nadja Ramhöj Holtryd, Madhavan Manivannan, Per Stenström, Miquel Pericàs
CBP: Coordinated management of cache partitioning, bandwidth partitioning and prefetch throttling. CoRR (2021)
Petros Voudouris, Per Stenström, Risat Pathan
Federated Scheduling of Sporadic DAGs on Unrelated Multiprocessors. ACM Trans. Embed. Comput. Syst. 20 (5s) (2021)
Nadja Ramhöj Holtryd, Madhavan Manivannan, Per Stenström, Miquel Pericàs
CBP: Coordinated management of cache partitioning, bandwidth partitioning and prefetch throttling. PACT (2021)
Nadja Holtryd, Madhavan Manivannan, Per Stenström, Miquel Pericàs
DELTA: Distributed Locality-Aware Cache Partitioning for Tile-based Chip Multiprocessors. IPDPS (2020)
Alexandra Angerd, Erik Sintorn, Per Stenström
A GPU Register File using Static Data Compression. CoRR (2020)
Alexandra Angerd, Erik Sintorn, Per Stenström
A GPU Register File using Static Data Compression. ICPP (2020)
Mehrzad Nejat, Madhavan Manivannan, Miquel Pericàs, Per Stenström
Coordinated management of DVFS and cache partitioning under QoS constraints to save energy in multi-core systems. J. Parallel Distributed Comput. 144 (2020)
Mehrzad Nejat, Madhavan Manivannan, Miquel Pericàs, Per Stenström
Coordinated Management of Processor Configuration and Cache Partitioning to Optimize Energy under QoS Constraints. IPDPS (2020)
Muhammad Waqar Azhar, Miquel Pericàs, Per Stenström
SaC: Exploiting Execution-Time Slack to Save Energy in Heterogeneous Multicore Systems. ICPP (2019)
Mehrzad Nejat, Madhavan Manivannan, Miquel Pericàs, Per Stenström
Coordinated Management of Processor Configuration and Cache Partitioning to Optimize Energy under QoS Constraints. CoRR (2019)
Alba de Melo, Jesús Carretero, Per Stenström, Sanjay Ranka, Eduard Ayguadé
Trends on heterogeneous and innovative hardware and software systems. J. Parallel Distributed Comput. 133 (2019)
Mehrzad Nejat, Miquel Pericàs, Per Stenström
QoS-Driven Coordinated Management of Resources to Save Energy in Multi-core Systems. IPDPS (2019)
Mehrzad Nejat, Madhavan Manivannan, Miquel Pericàs, Per Stenström
Coordinated Management of DVFS and Cache Partitioning under QoS Constraints to Save Energy in Multi-Core Systems. CoRR (2019)
Dmitry Knyaginin, Vassilis Papaefstathiou, Per Stenström
ProFess: A Probabilistic Hybrid Main Memory Management Framework for High Performance and Fairness. HPCA (2018)
Madhavan Manivannan, Miquel Pericàs, Vassilis Papaefstathiou, Per Stenström
Global Dead-Block Management for Task-Parallel Programs. ACM Trans. Archit. Code Optim. 15 (3) (2018)
Risat Pathan, Petros Voudouris, Per Stenström
Scheduling Parallel Real-Time Recurrent Tasks on Multicore Platforms. IEEE Trans. Parallel Distributed Syst. 29 (4) (2018)
Muhammad Waqar Azhar, Per Stenström, Vassilis Papaefstathiou
SLOOP: QoS-Supervised Loop Execution to Reduce Energy on Heterogeneous Architectures. ACM Trans. Archit. Code Optim. 14 (4) (2017)
Madhavan Manivannan, Miquel Pericàs, Vassilis Papaefstathiou, Per Stenström
Runtime-Assisted Global Cache Management for Task-Based Parallel Programs. IEEE Comput. Archit. Lett. 16 (2) (2017)
Dmitry Knyaginin, Per Stenström
Rock: a framework for pruning the design space of hybrid main memory systems. MEMSYS (2017)
Petros Voudouris, Per Stenström, Risat Pathan
Timing-Anomaly Free Dynamic Scheduling of Task-Based Parallel Applications. RTAS (2017)
Alexandra Angerd, Erik Sintorn, Per Stenström
A Framework for Automated and Controlled Floating-Point Accuracy Reduction in Graphics Applications on GPUs. ACM Trans. Archit. Code Optim. 14 (4) (2017)
Manolis Marazakis, John Goodacre, Didier Fuin, Paul M. Carpenter, John Thomson, Emil Matús, Antimo Bruno, Per Stenström, Jérôme Martin, Yves Durand, Isabelle Dor
EUROSERVER: Share-anything scale-out micro-server design. DATE (2016)
Per Stenström
2015 Maurice Wilkes Award Given to Christos Kozyrakis. IEEE Micro 36 (3) (2016)
Petros Voudouris, Per Stenström, Risat Pathan
Timing-anomaly free dynamic scheduling of task-based parallel applications. RTSS (2016)
Madhavan Manivannan, Vassilis Papaefstathiou, Miquel Pericàs, Per Stenström
RADAR: Runtime-assisted dead region management for last-level caches. HPCA (2016)
Minghua Li, Guancheng Chen, Qijun Wang, Yonghua Lin, H. Peter Hofstee, Per Stenström, Dian Zhou
PATer: A Hardware Prefetching Automatic Tuner on IBM POWER8 Processor. IEEE Comput. Archit. Lett. 15 (1) (2016)
Dmitry Knyaginin, Vassilis Papaefstathiou, Per Stenström
Adaptive Row Addressing for Cost-Efficient Parallel Memory Protocols in Large-Capacity Memories. MEMSYS (2016)
Jochen Hollmann, J. Rubén Titos Gil, Per Stenström
Enhancing Garbage Collection Synchronization Using Explicit Bit Barriers. ICPP (2015)
Angelos Arelakis, Fredrik Dahlgren, Per Stenström
HyComp: a hybrid cache compression method for selection of data-type-specific compression methods. MICRO (2015)
Tobias Fjalling, Per Stenström
Performance Impact of Batching Web-Application Requests Using Hot-Spot Processing on GPUs. IPDPS (2015)
Per Stenström
Effective resource management towards efficient computing. DATE (2014)
M. M. Waliullah, Per Stenström
Removal of Conflicts in Hardware Transactional Memory Systems. Int. J. Parallel Program. 42 (1) (2014)
Bhavishya Goel, J. Rubén Titos Gil, Anurag Negi, Sally A. McKee, Per Stenström
Performance and Energy Analysis of the Restricted Transactional Memory Implementation on Haswell. IPDPS (2014)
Angelos Arelakis, Per Stenström
A Case for a Value-Aware Cache. IEEE Comput. Archit. Lett. 13 (1) (2014)
Dmitry Knyaginin, Georgi Gaydadjiev, Per Stenström
Crystal: A Design-Time Resource Partitioning Method for Hybrid Main Memory. ICPP (2014)
Viktor K. Prasanna, Yves Robert, Per Stenström
Introduction to the JPDC special issue on Perspectives on Parallel and Distributed Processing. J. Parallel Distributed Comput. 74 (7) (2014)
Madhavan Manivannan, Per Stenström
Runtime-Guided Cache Coherence Optimizations in Multi-core Architectures. IPDPS (2014)
Angelos Arelakis, Per Stenström
: A statistical compression cache scheme. ISCA (2014)
Risat Mahmud Pathan, Per Stenström, Lars-Goran Green, Torbjorn Hult, Patrik Sandin
Overhead-aware temporal partitioning on multicore processors. RTAS (2014)
J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström
ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 25 (5) (2014)
Mafijul Md. Islam, Per Stenström
Characterizing and Exploiting Small-Value Memory Instructions. IEEE Trans. Computers 63 (7) (2014)
Alen Bardizbanyan, Peter Gavin, David B. Whalley, Magnus Själander, Per Larsson-Edefors, Sally A. McKee, Per Stenström
Improving data access efficiency by using a tagless access buffer (TAB). CGO (2013)
Madhavan Manivannan, Anurag Negi, Per Stenström
Efficient Forwarding of Producer-Consumer Data in Task-Based Programs. ICPP (2013)
Per Stenström
Keynote talk: Towards automatic resource management in parallel architectures. PACT (2013)
Michael J. Flynn, Oskar Mencer, Veljko M. Milutinovic, Goran Rakocevic, Per Stenström, Roman Trobec, Mateo Valero
Moving from petaflops to petadata. Commun. ACM 56 (5) (2013)
J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström
Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 24 (11) (2013)
Adrià Armejach, Anurag Negi, Adrián Cristal, Osman S. Unsal, Per Stenström, Tim Harris
HARP: Adaptive abort recurrence prediction for Hardware Transactional Memory. HiPC (2013)
Per Stenström, Koen De Bosschere
Introduction to the special issue on high-performance and embedded architectures and compilers. ACM Trans. Archit. Code Optim. 8 (4) (2012)
Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström
π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory. HPCA (2012)
Guancheng Chen, Per Stenström
Critical lock analysis: diagnosing critical section bottlenecks in multithreaded applications. SC (2012)
Anurag Negi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Per Stenström
Transactional prefetching: narrowing the window of contention in hardware transactional memory. PACT (2012)
Mafijul Md. Islam, Per Stenström
A unified approach to eliminate memory accesses early. CASES (2011)
J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström
ZEBRA: a data-centric, hybrid-policy hardware transactional memory design. ICS (2011)
Madhavan Manivannan, Ben H. H. Juurlink, Per Stenström
Implications of Merging Phases on Scalability of Multi-core Architectures. ICPP (2011)
Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström
The Impact of Non-coherent Buffers on Lazy Hardware Transactional Memory Systems. IPDPS Workshops (2011)
Madhavan Manivannan, Ben H. H. Juurlink, Per Stenström
Poster: implications of merging phases on scalability of multi-core architectures. ICS (2011)
Mridha-Mohammad Waliullah, Per Stenström
Classification and Elimination of Conflicts in Hardware Transactional Memory Systems. SBAC-PAD (2011)
Per Stenström, Doug Burger, Wen-mei W. Hwu, Vipin Kumar, Kunle Olukotun, David A. Padua, Burton Smith
Panel Statement. IPDPS (2011)
Anurag Negi, Per Stenström, J. Rubén Titos Gil, Manuel E. Acacio, José M. García
Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory. PACT (2011)
Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström
Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory. ICPP (2011)
Yehuda Afek, Ulrich Drepper, Pascal Felber, Christof Fetzer, Vincent Gramoli, Michael Hohmuth, Etienne Riviere, Per Stenström, Osman S. Unsal, Walther Maldonado, Derin Harmanci, Patrick Marlier, Stephan Diestelhorst, Martin Pohlack, Adrián Cristal, Ibrahim Hur, Aleksandar Dragojevic, Rachid Guerraoui, Michal Kapalka, Sasa Tomic, Guy Korland, Nir Shavit, Martin Nowack, Torvald Riegel
The Velox Transactional Memory Stack. IEEE Micro 30 (5) (2010)
Anurag Negi, M. M. Waliullah, Per Stenström
LV*: a class of lazy versioning HTMs for low-cost integration of transactional memory systems. IFMT (2010)
Mafijul Md. Islam, Per Stenström
Characterization and exploitation of narrow-width loads: the narrow-width cache approach. CASES (2010)
Anurag Negi, M. M. Waliullah, Per Stenström
: A low complexity lazy versioning HTM infrastructure. ICSAMOS (2010)
Jochen Hollmann, Per Stenström
Using Hoarding to Increase Availability in Shared File Systems. ACIS-ICIS (2009)
Martin Thuresson, Magnus Själander, Per Stenström
A Flexible Code Compression Scheme Using Partitioned Look-Up Tables. HiPEAC (2009)
Per Stenström, David B. Whalley
Introduction. Trans. High Perform. Embed. Archit. Compil. 2 (2009)
M. M. Waliullah, Per Stenström
Schemes for avoiding starvation in transactional memory systems. Concurr. Comput. Pract. Exp. 21 (7) (2009)
Md. Mafijul Islam, Per Stenström
Zero-Value Caches: Cancelling Loads that Return Zero. PACT (2009)
Martin Thuresson, Magnus Själander, Magnus Björk, Lars J. Svensson, Per Larsson-Edefors, Per Stenström
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. J. Signal Process. Syst. 57 (1) (2009)
Md. Mafijul Islam, Sally A. McKee, Per Stenström
Cancellation of loads that return zero using zero-value caches. ICS (2009)
Reinhard Wilhelm, Jakob Engblom, Andreas Ermedahl, Niklas Holsti, Stephan Thesing, David B. Whalley, Guillem Bernat, Christian Ferdinand, Reinhold Heckmann, Tulika Mitra, Frank Mueller, Isabelle Puaut, Peter P. Puschner, Jan Staschulat, Per Stenström
The worst-case execution-time problem - overview of methods and survey of tools. ACM Trans. Embed. Comput. Syst. 7 (3) (2008)
Fredrik Warg, Per Stenström
Dual-thread Speculation: A Simple Approach to Uncover Thread-level Parallelism on a Simultaneous Multithreaded Processor. Int. J. Parallel Program. 36 (2) (2008)
Jaeheon Jeong, Per Stenström, Michel Dubois
Simple Penalty-Sensitive Cache Replacement Policies. J. Instr. Level Parallelism 10 (2008)
Martin Thuresson, Lawrence Spracklen, Per Stenström
Memory-Link Compression Schemes: A Value Locality Perspective. IEEE Trans. Computers 57 (7) (2008)
M. M. Waliullah, Per Stenström
Efficient management of speculative data in hardware transactional memory systems. ICSAMOS (2008)
M. M. Waliullah, Per Stenström
Intermediate checkpointing with conflicting access prediction in transactional memory systems. IPDPS (2008)
Md. Mafijul Islam, Magnus Själander, Per Stenström
Early detection and bypassing of trivial operations to improve energy efficiency of processors. Microprocess. Microsystems 32 (4) (2008)
Martin Thuresson, Per Stenström
Accommodation of the Bandwidth of Large Cache Blocks Using Cache/Memory Link Compression. ICPP (2008)
Mafijul Md. Islam, Per Stenström
Zero loads: canceling load requests by tracking zero values. MEDEA@PACT (2008)
Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete, Per Stenström
Leveraging Data Promotion for Low Power D-NUCA Caches. DSD (2008)
Per Stenström
Introduction to Part 1. Trans. High Perform. Embed. Archit. Compil. 1 (2007)
Martin Thuresson, Magnus Själander, Magnus Björk, Lars J. Svensson, Per Larsson-Edefors, Per Stenström
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. ICSAMOS (2007)
Haakon Dybdahl, Per Stenström
An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors. HPCA (2007)
Per Stenström
IPDPS Panel: Is the Multi-Core Roadmap going to Live Up to its Promises? IPDPS (2007)
M. M. Waliullah, Per Stenström
Starvation-free commit arbitration policies for transactional memory systems. SIGARCH Comput. Archit. News 35 (1) (2007)
M. M. Waliullah, Per Stenström
Starvation-Free Transactional Memory-System Protocols. Euro-Par (2007)
Marco Galluzzi, Enrique Vallejo, Adrián Cristal, Fernando Vallejo, Ramón Beivide, Per Stenström, James E. Smith, Mateo Valero
Implicit Transactional Memory in Kilo-Instruction Multiprocessors. Asia-Pacific Computer Systems Architecture Conference (2007)
Jochen Hollmann, Anders Ardö, Per Stenström
Effectiveness of caching in a distributed digital library system. J. Syst. Archit. 53 (7) (2007)

Per Stenström.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Per Stenström