Fredrik Dahlgren

Publication Activity (10 Years)

Years Active: 1991-2015
Publications (10 Years): 0

Top Topics

Top Venues

Publications

Angelos Arelakis, Fredrik Dahlgren, Per Stenström
HyComp: a hybrid cache compression method for selection of data-type-specific compression methods. MICRO (2015)
Fredrik Dahlgren
Partial Continuous Functions and Admissible Domain Representations. J. Log. Comput. 17 (6) (2007)
Fredrik Dahlgren
Partial Continuous Functions and Admissible Domain Representations. CiE (2006)
Fredrik Dahlgren
Computability and continuity in metric partial algebras equipped with computability structures. Math. Log. Q. 50 (4-5) (2004)
Magnus Ekman, Per Stenström, Fredrik Dahlgren
TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors. ISLPED (2002)
Eduard Ayguadé, Fredrik Dahlgren, Christine Eisenbeis, Roger Espasa, Guang R. Gao, Henk L. Muller, Rizos Sakellariou, André Seznec
Topic 08+13: Instruction-Level Parallelism and Computer Architecture. Euro-Par (2001)
Fredrik Dahlgren
Future Mobile Phones - Complex Design Challenges from an Embedded Systems Perspective. ICECCS (2001)
Ashley Saulsbury, Fredrik Dahlgren, Per Stenström
Recency-based TLB preloading. ISCA (2000)
Magnus Karlsson, Fredrik Dahlgren, Per Stenström
A Prefetching Technique for Irregular Accesses to Linked Data Structures. HPCA (2000)
Martin Kämpe, Fredrik Dahlgren
Exploration of the Spatial Locality on Emerging Applications and the Consequences for Cache Performance. IPDPS (2000)
Jim Nilsson, Fredrik Dahlgren
Reducing Ownership Overhead for Load-Store Sequences in Cache-Coherent Multiprocessors. IPDPS (2000)
Jonas Skeppstedt, Fredrik Dahlgren, Per Stenström
Evaluation of Compiler-Controlled Updating to Reduce Coherence-Miss Penalties in Shared-Memory Multiprocessors. J. Parallel Distributed Comput. 56 (2) (1999)
Ashley Saulsbury, Su-Jaen Huang, Fredrik Dahlgren
Efficient management of memory hierarchies in embedded DRAM systems. International Conference on Supercomputing (1999)
Fredrik Dahlgren, Josep Torrellas
Cache-Only Memory Architectures. Computer 32 (6) (1999)
Fredrik Dahlgren
Techniques for Improving Performance of Hybrid Snooping Cache Protocols. J. Parallel Distributed Comput. 59 (3) (1999)
Jim Nilsson, Fredrik Dahlgren
Improving Performance of Load-Store Sequences for Transaction Processing Workloads on Multiprocessors. ICPP (1999)
Fredrik Dahlgren, Jonas Skeppstedt, Per Stenström
An evaluation of hardware-based and compiler-controlled optimizations of snooping cache protocols. Future Gener. Comput. Syst. 13 (6) (1998)
Fredrik Dahlgren, Michel Dubois, Per Stenström
Performance Evaluation and Cost Analysis of Cache Protocol Extensions for Shared-Memory Multiprocessors. IEEE Trans. Computers 47 (10) (1998)
Frederic T. Chong, Rajeev Barua, Fredrik Dahlgren, John Kubiatowicz, Anant Agarwal
The Sensitivity of Communication Mechanisms to Bandwidth and Latency. HPCA (1998)
Peter S. Magnusson, Fredrik Larsson, Andreas Moestedt, Bengt Werner, Jim Nilsson, Per Stenström, Fredrik Lundholm, Magnus Karlsson, Fredrik Dahlgren, Håkan Grahn
SimICS/Sun4m: A Virtual Workstation. USENIX Annual Technical Conference (1998)
Per Stenström, Fredrik Dahlgren
A holistic approach to computer system design education based on system simulation techniques. WCAE@ISCA (1998)
Fredrik Dahlgren, Per Stenström, Mårten Björkman
Reducing the Read-Miss Penalty for Flat COMA Protocols. Comput. J. 40 (4) (1997)
Per Stenström, Mats Brorsson, Fredrik Dahlgren, Håkan Grahn, Michel Dubois
Boosting the Performance of Shared Memory Multiprocessors. Computer 30 (7) (1997)
Fredrik Dahlgren, Anders Landin
Reducing the Replacement Overhead in Bus-Based COMA Multiprocessors. HPCA (1997)
Anders Landin, Fredrik Dahlgren
Bus-Based COMA - Reducing Traffic in Shared-Bus Multiprocessors. HPCA (1996)
Per Stenström, Fredrik Dahlgren
Applications for Shared Memory Multiprocessors (Guest Editors' Introduction). Computer 29 (12) (1996)
Fredrik Dahlgren, Per Stenström
Evaluation of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors. IEEE Trans. Parallel Distributed Syst. 7 (4) (1996)
Fredrik Dahlgren, Per Stenström
Effectiveness of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors. HPCA (1995)
Fredrik Dahlgren
Boosting the Performance of Hybrid Snooping Cache Protocols. ISCA (1995)
Mårten Björkman, Fredrik Dahlgren, Per Stenström
Using hints to reduce the read miss penalty for flat COMA protocols. HICSS (1) (1995)
Fredrik Dahlgren, Michel Dubois, Per Stenström
Sequential Hardware Prefetching in Shared-Memory Multiprocessors. IEEE Trans. Parallel Distributed Syst. 6 (7) (1995)
Fredrik Dahlgren, Per Stenström
Using Write Caches to Improve Performance of Cache Coherence Protocols in Shared-Memory Multiprocessors. J. Parallel Distributed Comput. 26 (2) (1995)
Fredrik Dahlgren, Michel Dubois, Per Stenström
Combined Performance Gains of Simple Cache Protocol Extensions. ISCA (1994)
Fredrik Dahlgren, Per Stenström
Reducing the Write Traffic for a Hybrid Cache Protocol. ICPP (1) (1994)
Mats Brorsson, Fredrik Dahlgren, Håkan Nilsson, Per Stenström
The Cachemire Test Bench A Flexible And Effective Approach For Simulation Of Multiprocessors. Annual Simulation Symposium (1993)
Fredrik Dahlgren, Michel Dubois, Per Stenström
Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors. ICPP (1) (1993)
Per Stenström, Fredrik Dahlgren, Lars Lundberg
A Lockup-Free Multiprocessor Cache Design. ICPP (1) (1991)
Fredrik Dahlgren
A program-driven simulation model of an MIMD multiprocessor. Annual Simulation Symposium (1991)
Fredrik Dahlgren, Per Stenström
On Reconfigurable On-Chip Data Caches. MICRO (1991)