André Seznec

ORCID

Publication Activity (10 Years)

Years Active: 1986-2024
Publications (10 Years): 36

Top Venues

ACM Trans. Archit. Code Optim.

MICRO

HPCA

SBAC-PAD

Publications

Bhargav Reddy Godala, Sankara Prasad Ramesh, Gilles A. Pokam, Jared Stark, André Seznec, Dean M. Tullsen, David I. August
PDIP: Priority Directed Instruction Prefetching. ASPLOS (2) (2024)
Daniel Rodrigues Carvalho, André Seznec
A Case for Partial Co-allocation Constraints in Compressed Caches. SAMOS (2021)
Kleovoulos Kalaitzidis, André Seznec
Leveraging Value Equality Prediction for Value Speculation. ACM Trans. Archit. Code Optim. 18 (1) (2021)
Daniel Rodrigues Carvalho, André Seznec
Conciliating Speed and Efficiency on Cache Compressors. ICCD (2021)
Daniel Rodrigues Carvalho, André Seznec
Understanding Cache Compression. ACM Trans. Archit. Code Optim. 18 (3) (2021)
Anita Tino, Caroline Collange, André Seznec
SIMT-X: Extending Single-Instruction Multi-Threading to Out-of-Order Cores. ACM Trans. Archit. Code Optim. 17 (2) (2020)
Niloofar Charmchi, Caroline Collange, André Seznec
Compressed Cache Layout Aware Prefetching. SBAC-PAD (2019)
Kleovoulos Kalaitzidis, André Seznec
Value Speculation through Equality Prediction. ICCD (2019)
Biswabandan Panda, André Seznec
Synergistic cache layout for reuse and compression. PACT (2018)
Arthur Perais, André Seznec
Cost effective speculation with the omnipredictor. PACT (2018)
Sajith Kalathingal, Sylvain Collange, Bharath Narasimha Swamy, André Seznec
DITVA: Dynamic Inter-Thread Vectorization Architecture. J. Parallel Distributed Comput. 120 (2018)
Fernando A. Endo, Arthur Perais, André Seznec
On the Interactions Between Value Prediction and Compiler Optimizations in the Context of EOLE. ACM Trans. Archit. Code Optim. 14 (2) (2017)
Arjun Suresh, Erven Rohou, André Seznec
Compile-time function memoization. CC (2017)
Aswinkumar Sridharan, Biswabandan Panda, André Seznec
Band-Pass Prefetching: An Effective Prefetch Management Mechanism Using Prefetch-Fraction Metric in Multi-Core Systems. ACM Trans. Archit. Code Optim. 14 (2) (2017)
Arthur Perais, André Seznec
Storage-Free Memory Dependency Prediction. IEEE Comput. Archit. Lett. 16 (2) (2017)
Aswinkumar Sridharan, André Seznec
Dynamic and discrete cache insertion policies for managing shared last level caches in large multicores. J. Parallel Distributed Comput. 106 (2017)
André Seznec, Joshua San Miguel, Jorge Albericio
Practical Multidimensional Branch Prediction. IEEE Micro 36 (3) (2016)
Biswabandan Panda, André Seznec
Dictionary sharing: An efficient cache compression scheme for compressed caches. MICRO (2016)
Arthur Perais, Fernando A. Endo, André Seznec
Register sharing for equality prediction. MICRO (2016)
Aswinkumar Sridharan, André Seznec
Discrete Cache Insertion Policies for Shared Last Level Cache Management on Large Multicores. IPDPS (2016)
Sajith Kalathingal, Sylvain Collange, Bharath Narasimha Swamy, André Seznec
Dynamic Inter-Thread Vectorization Architecture: Extracting DLP from TLP. SBAC-PAD (2016)
Arthur Perais, André Seznec
EOLE: Combining Static and Dynamic Scheduling Through Value Prediction to Reduce Complexity and Increase Performance. ACM Trans. Comput. Syst. 34 (2) (2016)
Arthur Perais, André Seznec
Cost effective physical register sharing. HPCA (2016)
Somayeh Sardashti, André Seznec, David A. Wood
Yet Another Compressed Cache: A Low-Cost Yet Effective Compressed Cache. ACM Trans. Archit. Code Optim. 13 (3) (2016)
Arthur Perais, André Seznec
EOLE: Toward a Practical Implementation of Value Prediction. IEEE Micro 35 (3) (2015)
Misel-Myrto Papadopoulou, Xin Tong, André Seznec, Andreas Moshovos
Prediction-based superpage-friendly TLB designs. HPCA (2015)
Andreas Sembrant, Trevor E. Carlson, Erik Hagersten, David Black-Schaffer, Arthur Perais, André Seznec, Pierre Michaud
Long term parking (LTP): criticality-aware resource allocation in OOO processors. MICRO (2015)
Arthur Perais, André Seznec
BeBoP: A cost effective predictor infrastructure for superscalar value prediction. HPCA (2015)
Arthur Perais, André Seznec, Pierre Michaud, Andreas Sembrant, Erik Hagersten
Cost-effective speculative scheduling in high performance processors. ISCA (2015)
Erven Rohou, Bharath Narasimha Swamy, André Seznec
Branch prediction and the performance of interpreters: don't trust folklore. CGO (2015)
André Seznec, Joshua San Miguel, Jorge Albericio
The inner most loop iteration counter: a new dimension in branch history. MICRO (2015)
Surya Narayanan, Bharath Narasimha Swamy, André Seznec
An empirical high level performance model for future many-cores. Conf. Computing Frontiers (2015)
Surya Narayanan, André Seznec
Sequential and Parallel Code Sections are Different: they may require different Processors. PARMA-DITAM@HiPEAC (2015)
Pierre Michaud, Andrea Mondelli, André Seznec
Revisiting Clustered Microarchitecture for Future Superscalar Cores: A Case for Wide Issue Clusters. ACM Trans. Archit. Code Optim. 12 (3) (2015)
Arjun Suresh, Bharath Narasimha Swamy, Erven Rohou, André Seznec
Intercepting Functions for Memoization: A Case Study Using Transcendental Functions. ACM Trans. Archit. Code Optim. 12 (2) (2015)
Ricardo A. Velásquez, Pierre Michaud, André Seznec
BADCO: Behavioral Application-Dependent Superscalar Core Models. Int. J. Parallel Program. 43 (1) (2015)
Arthur Perais, André Seznec
Practical data value speculation for future high-end processors. HPCA (2014)
Bharath Narasimha Swamy, Alain Ketterlin, André Seznec
Hardware/Software Helper Thread Prefetching on Heterogeneous Many Cores. SBAC-PAD (2014)
Surya Narayanan, Bharath Narasimha Swamy, André Seznec
Impact of Serial Scaling of Multi-threaded Programs in Many-Core Era. SBAC-PAD (Workshops) (2014)
Nathanaël Prémillieu, André Seznec
Efficient Out-of-Order Execution of Guarded ISAs. ACM Trans. Archit. Code Optim. 11 (4) (2014)
Arthur Perais, André Seznec
EOLE: Paving the way for an effective implementation of value prediction. ISCA (2014)
Somayeh Sardashti, André Seznec, David A. Wood
Skewed Compressed Caches. MICRO (2014)
Ricardo A. Velásquez, Pierre Michaud, André Seznec
Selecting benchmark combinations for the evaluation of multicore throughput. ISPASS (2013)
André Seznec
Faster unicores are still needed. ICSAMOS (2013)
Junjie Lai, André Seznec
Performance upper bound analysis and optimization of SGEMM on Fermi and Kepler GPUs. CGO (2013)
André Seznec, François Bodin
Message from the program chairs. PACT (2013)
Nathanaël Prémillieu, André Seznec
SYRANT: SYmmetric resource allocation on not-taken and taken paths. ACM Trans. Archit. Code Optim. 8 (4) (2012)
Benjamin Lesage, Isabelle Puaut, André Seznec
PRETI: partitioned real-time shared cache for mixed-criticality real-time systems. RTNS (2012)
Ricardo A. Velásquez, Pierre Michaud, André Seznec
BADCO: Behavioral Application-Dependent Superscalar Core model. ICSAMOS (2012)
Junjie Lai, André Seznec
Break down GPU execution time with an analytical method. RAPIDO (2012)
Julien Dusser, André Seznec
Decoupled zero-compressed memory. HiPEAC (2011)
André Seznec
Storage free confidence estimation for the TAGE branch predictor. HPCA (2011)
André Seznec
A new case for the TAGE branch predictor. MICRO (2011)
Hans Vandierendonck, André Seznec
Managing SMT resource usage through speculative instruction window weighting. ACM Trans. Archit. Code Optim. 8 (3) (2011)
Moinuddin K. Qureshi, André Seznec, Luis A. Lastras, Michele Franceschini
Practical and secure PCM systems by online detection of malicious write streams. HPCA (2011)
Hans Vandierendonck, André Seznec
Fairness Metrics for Multi-Threaded Processors. IEEE Comput. Archit. Lett. 10 (1) (2011)
Pierre Michaud, Yiannakis Sazeides, André Seznec
Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses. Conf. Computing Frontiers (2010)
André Seznec
A Phase Change Memory as a Secure Main Memory. IEEE Comput. Archit. Lett. 9 (1) (2010)
Alin Suciu, Tudor Carean, André Seznec, Kinga Marton
Parallel HAVEGE. PPAM (2) (2009)
Julien Dusser, Thomas Piquet, André Seznec
Zero-content augmented caches. ICS (2009)
Hans Vandierendonck, André Seznec
Fetch Gating Control through Speculative Instruction Window Weighting. Trans. High Perform. Embed. Archit. Compil. 2 (2009)
Hans Vandierendonck, André Seznec
Speculative return address stack management revisited. ACM Trans. Archit. Code Optim. 5 (3) (2008)
André Seznec
The L-TAGE Branch Predictor. J. Instr. Level Parallelism 9 (2007)
Hans Vandierendonck, André Seznec
Fetch Gating Control Through Speculative Instruction Window Weighting. HiPEAC (2007)
André Seznec
The Idealistic GTL Predictor. J. Instr. Level Parallelism 9 (2007)
Thomas Piquet, Olivier Rochecouste, André Seznec
Exploiting Single-Usage for Effective Memory Management. Asia-Pacific Computer Systems Architecture Conference (2007)
Koen De Bosschere, Wayne Luk, Xavier Martorell, Nacho Navarro, Michael F. P. O'Boyle, Dionisios N. Pnevmatikatos, Alex Ramírez, Pascal Sainrat, André Seznec, Per Stenström, Olivier Temam
High-Performance Embedded Architecture and Compilation Roadmap. Trans. High Perform. Embed. Archit. Compil. 1 (2007)
Pierre Michaud, André Seznec, Damien Fetis, Yiannakis Sazeides, Theofanis Constantinou
A study of thread migration in temperature-constrained multicores. ACM Trans. Archit. Code Optim. 4 (2) (2007)
André Seznec, Pierre Michaud
A case for (partially) TAgged GEometric history length branch prediction. J. Instr. Level Parallelism 8 (2006)
Olivier Rochecouste, Gilles Pokam, André Seznec
A case for a complexity-effective, width-partitioned microarchitecture. ACM Trans. Archit. Code Optim. 3 (3) (2006)
André Seznec, Roger Espasa
Conflict-Free Accesses to Strided Vectors on a Banked Cache. IEEE Trans. Computers 54 (7) (2005)
Julio César Hernández Castro, José María Sierra, André Seznec, Antonio Izquierdo, Arturo Ribagorda
The strict avalanche criterion randomness test. Math. Comput. Simul. 68 (1) (2005)
Theofanis Constantinou, Yiannakis Sazeides, Pierre Michaud, Damien Fetis, André Seznec
Performance implications of single thread migration on a chip multi-core. SIGARCH Comput. Archit. News 33 (4) (2005)
André Seznec
Genesis of the O-GEHL Branch Predictor. J. Instr. Level Parallelism 7 (2005)
André Seznec
Analysis of the O-GEometric History Length Branch Predictor. ISCA (2005)
André Seznec
Concurrent Support of Multiple Page Sizes on a Skewed Associative TLB. IEEE Trans. Computers 53 (7) (2004)
Gilles Pokam, Olivier Rochecouste, André Seznec, François Bodin
Speculative software management of datapath-width for energy optimization. LCTES (2004)
Kemal Ebcioglu, Wolfgang Karl, André Seznec, Marco Aldinucci
Topic 8: Parallel Computer Architecture and Instruction-Level Parallelism. Euro-Par (2004)
Julio César Hernández Castro, André Seznec, Pedro Isasi
On the design of state-of-the-art pseudorandom number generators by means of genetic programming. IEEE Congress on Evolutionary Computation (2004)
Julio César Hernández Castro, José María Sierra, André Seznec
The SAC Test: A New Randomness Test, with Some Applications to PRNG Analysis. ICCSA (1) (2004)
Romain Dolbeau, André Seznec
CASH: Revisiting Hardware Sharing in Single-Chip Parallel Processors. J. Instr. Level Parallelism 6 (2004)
Amaury Darsch, André Seznec
IATO: A Flexible EPIC Simulation Environment. SBAC-PAD (2004)
André Seznec, Antony Fraboulet
Effective ahead Pipelining of Instruction Block Address Generation. ISCA (2003)
André Seznec, Nicolas Sendrier
HAVEGE: A user-level software heuristic for generating empirically strong random numbers. ACM Trans. Model. Comput. Simul. 13 (4) (2003)
André Seznec, Eric Toullec, Olivier Rochecouste
Register write specialization register read specialization: a path to complexity-effective wide-issue superscalar processors. MICRO (2002)
André Seznec, Stephen Felix, Venkata Krishnan, Yiannakis Sazeides
Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor. ISCA (2002)
Roger Espasa, Federico Ardanaz, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Joel S. Emer, Stephen Felix, P. Geoffrey Lowney, Matthew Mattina, André Seznec
Tarantula: A Vector Extension to the Alpha Architecture. ISCA (2002)
Eduard Ayguadé, Fredrik Dahlgren, Christine Eisenbeis, Roger Espasa, Guang R. Gao, Henk L. Muller, Rizos Sakellariou, André Seznec
Topic 08+13: Instruction-Level Parallelism and Computer Architecture. Euro-Par (2001)
Pierre Michaud, André Seznec, Stéphan Jourdan
An Exploration of Instruction Fetch Requirement in Out-of-Order Superscalar Processors. Int. J. Parallel Program. 29 (1) (2001)
Kun Luo, Manoj Franklin, Shubhendu S. Mukherjee, André Seznec
Boosting SMT Performance by Speculation Control. IPDPS (2001)
Pierre Michaud, André Seznec
Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors. HPCA (2001)
Thierry Lafage, André Seznec
Combining Light Static Code Annotation and Instruction-Set Emulation for Flexible and Efficient On-the-Fly Simulation (Research Note). Euro-Par (2000)
Erven Rohou, François Bodin, Christine Eisenbeis, André Seznec
Handling Global Constraints in Compiler Strategy. Int. J. Parallel Program. 28 (4) (2000)
Michel Barreteau, François Bodin, Zbigniew Chamski, Henri-Pierre Charles, Christine Eisenbeis, John R. Gurd, Jan Hoogerbrugge, Ping Hu, William Jalby, Toru Kisuki, Peter M. W. Knijnenburg, Paul van der Mark, Andy Nisbet, Michael F. P. O'Boyle, Erven Rohou, André Seznec, Elena Stöhr, Menno Treffers, Harry A. G. Wijshoff
OCEANS - Optimising Compilers for Embedded Applications. Euro-Par (1999)
Pierre Michaud, André Seznec, Stéphan Jourdan
Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors. IEEE PACT (1999)
Sébastien Hily, André Seznec
Out-of-Order Execution may not be Cost-Effective on Processors Featuring Simultaneous Multithreading. HPCA (1999)
Thierry Lafage, André Seznec, Erven Rohou, François Bodin
Code Cloning Tracing: A "Pay per Trace" Approach. Euro-Par (1999)
Michel Barreteau, François Bodin, Peter Brinkhaus, Zbigniew Chamski, Henri-Pierre Charles, Christine Eisenbeis, John R. Gurd, Jan Hoogerbrugge, Ping Hu, William Jalby, Peter M. W. Knijnenburg, Michael F. P. O'Boyle, Erven Rohou, Rizos Sakellariou, André Seznec, Elena Stöhr, Menno Treffers, Harry A. G. Wijshoff
OCEANS: Optimising Compilers for Embedded Applications. Euro-Par (1998)
D. N. Truong, François Bodin, André Seznec
Improving Cache Behavior of Dynamically Allocated Data Structures. IEEE PACT (1998)
Pierre Michaud, André Seznec, Richard Uhlig
Trading Conflict and Capacity Aliasing in Conditional Branch Predictors. ISCA (1997)

André Seznec.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

André Seznec