Intelligent Memory Systems

Keyphrases

Publications

volume 2107, 2001

Intelligent Memory Systems, Second International Workshop, IMS 2000, Cambridge, MA, USA, November 12, 2000, Revised Papers Intelligent Memory Systems 2107 (2001)

2000

Peter Grun, Nikil D. Dutt, Alexandru Nicolau
Aggressive Memory-Aware Compilation. Intelligent Memory Systems (2000)
David Judd, Katherine A. Yelick, Christoforos E. Kozyrakis, David R. Martin, David A. Patterson
Exploiting On-Chip Memory Bandwidth in the VIRAM Compiler. Intelligent Memory Systems (2000)
Tsung-Chuan Huang, Slo-Li Chu
SAGE: A New Analysis and Optimization System for FlexRAM Architecture. Intelligent Memory Systems (2000)
Dan Nicolaescu, Xiaomei Ji, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta
Compiler-Directed Cache Line Size Adaptivity. Intelligent Memory Systems (2000)
Richard C. Murphy, Peter M. Kogge, Arun Rodrigues
The Characterization of Data Intensive Memory Workloads on Distributed PIM Systems. Intelligent Memory Systems (2000)
Robert Cooksey, Dennis Colarelli, Dirk Grunwald
Content-Based Prefetching: Initial Results. Intelligent Memory Systems (2000)
Hiroshi Nakamura, Masaaki Kondo, Taisuke Boku
Software Controlled Reconfigurable On-Chip Memory for High Performance Computing. Intelligent Memory Systems (2000)
Lixin Zhang, Venkata K. Pingali, Bharat Chandramouli, John B. Carter
Memory System Support for Dynamic Cache Line Assembly. Intelligent Memory Systems (2000)
Mary W. Hall, Craig S. Steele
Memory Management in a PIM-Based Architecture. Intelligent Memory Systems (2000)
Yan Solihin, Jaejin Lee, Josep Torrellas
Adaptively Mapping Code in an Intelligent Memory Architecture. Intelligent Memory Systems (2000)
Jeff La Coss
The DIVA Emulator: Accelerating Architecture Studies for PIM-Based Systems. Intelligent Memory Systems (2000)
Csaba Andras Moritz, Matthew I. Frank, Saman P. Amarasinghe
FlexCache: A Framework for Flexible Compiler Generated Data Caching. Intelligent Memory Systems (2000)
Junji Ogawa, Mark Horowitz
A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro. Intelligent Memory Systems (2000)
Workshop Notes. Intelligent Memory Systems (2000)
Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips. Intelligent Memory Systems (2000)
Koji Inoue, Koji Kai, Kazuaki J. Murakami
Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems. Intelligent Memory Systems (2000)