Mohammad Hosseinabady

Publication Activity (10 Years)

Years Active: 2003-2021
Publications (10 Years): 17

Top Topics

Matrix Multiplication

Embedded Systems

Top Venues

IET Comput. Digit. Tech.

PARMA-DITAM@HiPEAC

Publications

José L. Núñez-Yáñez, Mohammad Hosseinabady
Sparse and dense matrix multiplication hardware for heterogeneous multi-precision neural networks. Array 12 (2021)
Mohammad Hosseinabady, José L. Núñez-Yáñez
Sparse Matrix-Dense Matrix Multiplication on Heterogeneous CPU+FPGA Embedded System. PARMA-DITAM@HiPEAC (2020)
José L. Núñez-Yáñez, Kris Nikov, Kerstin Eder, Mohammad Hosseinabady
Run-Time Power Modelling in Embedded GPUs with Dynamic Voltage and Frequency Scaling. PARMA-DITAM@HiPEAC (2020)
Mohammad Hosseinabady, José Luis Núñez-Yáñez
A Streaming Dataflow Engine for Sparse Matrix-Vector Multiplication Using High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (6) (2020)
Kris Nikov, Mohammad Hosseinabady, Rafael Asenjo, Andrés Rodríguez, Angeles G. Navarro, José L. Núñez-Yáñez
High-Performance Simultaneous Multiprocessing for Heterogeneous System-on-Chip. CoRR (2020)
José L. Núñez-Yáñez, Kris Nikov, Kerstin Eder, Mohammad Hosseinabady
Run-Time Power Modelling in Embedded GPUs with Dynamic Voltage and Frequency Scaling. CoRR (2020)
José L. Núñez-Yáñez, Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Darío Suárez Gracia, Ruben Gran
Simultaneous multiprocessing in a software-defined heterogeneous FPGA. J. Supercomput. 75 (8) (2019)
José L. Núñez-Yáñez, Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Darío Suárez Gracia, Ruben Gran
Correction to: Simultaneous multiprocessing in a software-defined heterogeneous FPGA. J. Supercomput. 75 (8) (2019)
Mohammad Hosseinabady, Mohd Amiruddin Bin Zainol, José L. Núñez-Yáñez
Heterogeneous FPGA+GPU Embedded Systems: Challenges and Opportunities. CoRR (2019)
Mohammad Hosseinabady, José Luis Núñez-Yáñez
Dynamic Energy Management of FPGA Accelerators in Embedded Systems. ACM Trans. Embed. Comput. Syst. 17 (3) (2018)
Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, José L. Núñez-Yáñez
Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips. FPL (2018)
Sam Amiri, Mohammad Hosseinabady, Simon McIntosh-Smith, José L. Núñez-Yáñez
Multi-precision convolutional neural networks on heterogeneous hardware. DATE (2018)
José L. Núñez-Yáñez, Mohammad Hosseinabady, Moslem Amiri, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Ruben Gran Tejero, Darío Suárez Gracia
Parallelizing Workload Execution in Embedded and High-Performance Heterogeneous Systems. CoRR (2018)
Mohammad Hosseinabady, José Luis Núñez-Yáñez
A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis. FPL (2017)
Mohammad Hosseinabady, José Luis Núñez-Yáñez
Pipelined Streaming Computation of Histogram in FPGA OpenCL. PARCO (2017)
José L. Núñez-Yáñez, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Ruben Gran Tejero, Darío Suárez Gracia
Simultaneous Multiprocessing on a FPGA+CPU Heterogeneous System-On-Chip. PARCO (2017)
José Luis Núñez-Yáñez, Mohammad Hosseinabady, Arash Beldachi
Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling. IEEE Trans. Computers 65 (5) (2016)
Mohammad Hosseinabady, José Luis Núñez-Yáñez
Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices. FPL (2015)
Mohammad Hosseinabady, José Luis Núñez-Yáñez
Energy optimization of FPGA-based stream-oriented computing with power gating. FPL (2015)
Mohammad Hosseinabady, José Luis Núñez-Yáñez
Run-time power gating in hybrid ARM-FPGA devices. FPL (2014)
Mohammad Hosseinabady, José Luis Núñez-Yáñez
Fast and low overhead architectural transaction level modelling for large-scale network-on-chip simulation. IET Comput. Digit. Tech. 6 (6) (2012)
José L. Núñez-Yáñez, Arash Beldachi, Atukem Nabina, Mohammad Hosseinabady
Exploring dynamically reconfigurable multicore designs with NoRC designer. HPCS (2012)
Mohammad Hosseinabady, José Luis Núñez-Yáñez
Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles. IET Comput. Digit. Tech. 6 (1) (2012)
Mohammad Hosseinabady, Pejman Lotfi-Kamran, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan
Single-Event Transient Analysis in High Speed Circuits. ISED (2011)
Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan
Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph. IEEE Trans. Very Large Scale Integr. Syst. 19 (8) (2011)
Mohammad Hosseinabady, José Luis Núñez-Yáñez, Antonio Marcello Coppola
Task Dispersal Measurement in Dynamic Reconfigurable NoCs. ISVLSI (2010)
Mohammad Hosseinabady, José L. Núñez-Yáñez
SystemC Architectural Transaction Level Modelling for Large NoCs. FDL (2010)
Mohammad Hosseinabady, José L. Núñez-Yáñez
Effective modelling of large NoCs using SystemC. ISCAS (2010)
José L. Núñez-Yáñez, Mohammad Hosseinabady, Atukem Nabina, Izhar Zaidi
Energy optimization in a Network-on-Chip with dynamically reconfigurable processing nodes. CCA/ISIC (2009)
Mohammad Hosseinabady, José L. Núñez-Yáñez
Run-time resource management in fault-tolerant network on reconfigurable chips. FPL (2009)
Mohammad Hosseinabady, José L. Núñez-Yáñez
Fault-tolerant dynamically reconfigurable NoC-based SoC. ASAP (2008)
Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan
De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs. DATE (2008)
Mohammad Hosseinabady, Shervin Sharifi, Fabrizio Lombardi, Zainalabedin Navabi
A Selective Trigger Scan Architecture for VLSI Testing. IEEE Trans. Computers 57 (3) (2008)
Jimson Mathew, Jawar Singh, Abusaleh M. Jabir, Mohammad Hosseinabady, Dhiraj K. Pradhan
Fault tolerant bit parallel finite field multipliers using LDPC codes. ISCAS (2008)
Mohammad Hosseinabady, Atefe Dalirsani, Zainalabedin Navabi
Using the inter- and intra-switch regularity in NoC switch testing. DATE (2007)
Jawar Singh, Jimson Mathew, Mohammad Hosseinabady, Dhiraj K. Pradhan
Single Event Upset Detection and Correction. ICIT (2007)
Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi
Simultaneous Reduction of Dynamic and Static Power in Scan Structures CoRR (2007)
Mohammad Hosseinabady, Pejman Lotfi-Kamran, Zainalabedin Navabi
Low test application time resource binding for behavioral synthesis. ACM Trans. Design Autom. Electr. Syst. 12 (2) (2007)
Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Giorgio Di Natale
Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC. IOLTS (2007)
Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan
Reliable network-on-chip based on generalized de Bruijn graph. HLDVT (2007)
Atefe Dalirsani, Mohammad Hosseinabady, Zainalabedin Navabi
An Analytical Model for Reliability Evaluation of NoC Architectures. IOLTS (2007)
Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Pejman Lotfi-Kamran, Zainalabedin Navabi
A UML Based System Level Failure Rate Assessment Technique for SoC Designs. VTS (2007)
Mohammad Hosseinabady, Pejman Lotfi-Kamran, Fabrizio Lombardi, Zainalabedin Navabi
Low overhead DFT using CDFG by modifying controller. IET Comput. Digit. Tech. 1 (4) (2007)
Mohammad Hosseinabady, Abbas Banaiyan, Mahdi Nazm Bojnordi, Zainalabedin Navabi
A concurrent testing method for NoC switches. DATE (2006)
Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi
Scan-Based Structure with Reduced Static and Dynamic Power Consumption. J. Low Power Electron. 2 (3) (2006)
Mohammad Hosseinabady, Pejman Lotfi-Kamran, Giorgio Di Natale, Stefano Di Carlo, Alfredo Benso, Paolo Prinetto
Single-Event Upset Analysis and Protection in High Speed Circuits. ETS (2006)
Mohammad Hosseinabady, Pejman Lotfi-Kamran, Pedram A. Riahi, Fabrizio Lombardi, Zainalabedin Navabi
A Flow Graph Technique for DFT Controller Modification. SoCC (2005)
Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi
Simultaneous Reduction of Dynamic and Static Power in Scan Structures. DATE (2005)
Pejman Lotfi-Kamran, Mohammad Hosseinabady, Hamid Shojaei, Mehran Massoumi, Zainalabedin Navabi
TED+: a data structure for microprocessor verification. ASP-DAC (2005)
Shervin Sharifi, Mohammad Hosseinabady, Zainalabedin Navabi
Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing. VLSI-SOC (2003)
Shervin Sharifi, Mohammad Hosseinabady, Pedram A. Riahi, Zainalabedin Navabi
Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture. DFT (2003)