A Selective Trigger Scan Architecture for VLSI Testing.
Mohammad HosseinabadyShervin SharifiFabrizio LombardiZainalabedin NavabiPublished in: IEEE Trans. Computers (2008)
Keyphrases
- management system
- processor array
- vlsi implementation
- vlsi architecture
- high speed
- signal processing
- real time
- distributed architecture
- test set
- layered architecture
- vlsi design
- hardware architecture
- architectural design
- design considerations
- software architecture
- control system
- knowledge base
- information systems
- computer vision
- learning algorithm
- genetic algorithm
- machine learning