Jawar Singh

ORCID

Publication Activity (10 Years)

Years Active: 2007-2024
Publications (10 Years): 21

Top Venues

University of Bristol, UK (PHD)

Education History

University of Bristol, UK

PHD

Publications

V. Bharath Sreenivasulu, Aruna Kumari Neelam, Asisa Kumar Panigrahy, Lokesh Vakkalakula, Jawar Singh, Shiv Govind Singh
Benchmarking of Multi-Bridge-Channel FETs Toward Analog and Mixed-Mode Circuit Applications. IEEE Access 12 (2024)
V. Bharath Sreenivasulu, Aruna Kumari Neelam, Sekhar Reddy Kola, Jawar Singh, Yiming Li
Exploring the Performance of 3-D Nanosheet FET in Inversion and Junctionless Modes: Device and Circuit-Level Analysis and Comparison. IEEE Access 11 (2023)
Abhash Kumar, Sai Manohar Beeraka, Jawar Singh, Bharat Gupta
An On-Chip Trainable and Scalable In-Memory ANN Architecture for AI/ML Applications. Circuits Syst. Signal Process. 42 (5) (2023)
Ankit Sirohi, Jawar Singh
A Steep Slope Sub-10nm Armchair Phosphorene Nanoribbon FET with Intrinsic Cold Contact. VLSI-SoC (2023)
Swati, Sangita Roy, Jawar Singh, Jimson Mathew
Design and analysis of DDoS mitigating network architecture. Int. J. Inf. Sec. 22 (2) (2023)
Kota Nikhileswar, Sudhir Kumar, Jawar Singh, Dharmendra Muthuswamy
A Framework for the Automation of Platform Validation for Use Cases of Wi-Fi. ICIT (2022)
Bhavye Sharma, Raju Halder, Jawar Singh
Blockchain-based Interoperable Healthcare using Zero-Knowledge Proofs and Proxy Re-Encryption. COMSNETS (2020)
Abhash Kumar, Jawar Singh, Sai Manohar Beeraka, Bharat Gupta
In-memory Implementation of On-chip Trainable and Scalable ANN for AI/ML Applications. CoRR (2020)
Alok Kumar Kamal, Jawar Singh
Ultra-Low Energy and High Speed LIF Neuron using Silicon Bipolar Impact Ionization MOSFET for Spiking Neural Networks. CoRR (2019)
Ankit Sirohi, Chitrakant Sahu, Jawar Singh
Analog/RF Performance Investigation of Dopingless FET for Ultra-Low Power Applications. IEEE Access 7 (2019)
Md. Hasan Raza Ansari, Jawar Singh
Improvement in Retention Time of Capacitorless DRAM with Access Transistor. CoRR (2019)
Venkata P. Yanambaka, Saraju P. Mohanty, Elias Kougianos, Prabha Sundaravadivel, Jawar Singh
Dopingless Transistor Based Hybrid Oscillator Arbiter Physical Unclonable Function. ISVLSI (2017)
Venkata P. Yanambaka, Saraju P. Mohanty, Elias Kougianos, Prabha Sundaravadivel, Jawar Singh
Reconfigurable Robust Hybrid Oscillator Arbiter PUF for IoT Security Based on DL-FET. ISVLSI (2017)
Nawaz Shafi, Chitrakant Sahu, C. Periasamy, Jawar Singh
SiGe Source Charge Plasma TFET for Biosensing Applications. iNIS (2017)
Chaitanya Maradana, Jawar Singh
Proposal of Heterogate Technique for Performance Enhancement of DM-TFET. iNIS (2016)
Meena Panchore, Jawar Singh, Saraju P. Mohanty, Elias Kougianos
Compact Behavioral Modeling and Time Dependent Performance Degradation Analysis of Junction and Doping Free Transistors. iNIS (2016)
Venkata P. Yanambaka, Saraju P. Mohanty, Elias Kougianos, Jawar Singh
Secure Multi-key Generation Using Ring Oscillator Based Physical Unclonable Function. iNIS (2016)
Muhammad Khalid, Jawar Singh
Memristor Crossbar-Based Pattern Recognition Circuit Using Perceptron Learning Rule. iNIS (2016)
Lokesh Kumar Bramhane, Jawar Singh
Extended Base Schottky-Collector Bipolar Charge Plasma Transistor. iNIS (2015)
Sunil Kumar Pandey, Jawar Singh
A low power and high gain CMOS LNA for UWB applications in 90 nm CMOS process. Microelectron. J. 46 (5) (2015)
Kanchan Cecil, Jawar Singh
Performance Enhancement of Dopingless Tunnel-FET Based on Ge-Source with High-k. iNIS (2015)
Deep Kishore Parsediya, Jawar Singh, Pavan Kumar Kankar
Modeling and simulation of variable thickness based stepped MEMS cantilever designs for biosensing and pull-in voltage optimization. VDAT (2014)
Anup Shrivastava, Jawar Singh
Dual-sided doped memristor and it's SPICE modelling for improved electrical properties. ISQED (2014)
Komal Singh, Chitrakant Sahu, Jawar Singh
Linearly separable pattern classification using memristive crossbar circuits. ISQED (2014)
Sachin Agrawal, Sunil Kumar Pandey, Jawar Singh, Manoj Singh Parihar
Realization of efficient RF energy harvesting circuits employing different matching technique. ISQED (2014)
Jawar Singh, N. Vijaykrishnan
A highly reliable NBTI Resilient 6T SRAM cell. Microelectron. Reliab. 53 (4) (2013)
Anup Shrivastava, Jawar Singh
Dual sided doped memristor and it's mathematical modelling. ICECS (2013)
Sachin Agrawal, Sunil Kumar Pandey, Jawar Singh, Pravin Neminath Kondekar
An Efficient RF Energy Harvester with Tuned Matching Circuit. VDAT (2013)
G. K. Reddy, Kapil Jainwal, Jawar Singh, Saraju P. Mohanty
Process variation tolerant 9T SRAM bitcell design. ISQED (2012)
Saraju P. Mohanty, Jawar Singh, Elias Kougianos, Dhiraj K. Pradhan
Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM. Integr. 45 (1) (2012)
Jawar Singh, Krishnan Ramakrishnan, Saurabh Mookerjea, Suman Datta, Narayanan Vijaykrishnan, Dhiraj K. Pradhan
applications. ASP-DAC (2010)
Andrew J. Ricketts, Jawar Singh, Krishnan Ramakrishnan, Narayanan Vijaykrishnan, Dhiraj K. Pradhan
Investigating the impact of NBTI on different power saving cache strategies. DATE (2010)
Jawar Singh, Dilip S. Aswar, Saraju P. Mohanty, Dhiraj K. Pradhan
A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead. ISQED (2010)
Jawar Singh, Dhiraj K. Pradhan, Simon Hollis, Saraju P. Mohanty, Jimson Mathew
Single ended 6T SRAM with isolated read-port for low-power embedded systems. DATE (2009)
Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan
Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems. VLSI Design (2009)
Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty
A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies. SoCC (2008)
Jimson Mathew, Jawar Singh, Anas Abu Taleb, Dhiraj K. Pradhan
Fault Tolerant Reversible Finite Field Arithmetic Circuits. IOLTS (2008)
Yi Xin Su, Jimson Mathew, Jawar Singh, Dhiraj K. Pradhan
Pseudo parallel architecture for AES with error correction. SoCC (2008)
Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty
Failure analysis for ultra low power nano-CMOS SRAM under process variations. SoCC (2008)
Jimson Mathew, Jawar Singh, Abusaleh M. Jabir, Mohammad Hosseinabady, Dhiraj K. Pradhan
Fault tolerant bit parallel finite field multipliers using LDPC codes. ISCAS (2008)
Jawar Singh, Dhiraj K. Pradhan, Simon Hollis, Saraju P. Mohanty
A single ended 6T SRAM cell design for ultra-low-voltage applications. IEICE Electron. Express 5 (18) (2008)
Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan
A nano-CMOS process variation induced read failure tolerant SRAM cell. ISCAS (2008)
Jawar Singh, Jimson Mathew, Mohammad Hosseinabady, Dhiraj K. Pradhan
Single Event Upset Detection and Correction. ICIT (2007)
Babita R. Jose, P. Mythili, Jawar Singh, Jimson Mathew
A Triple-Mode Sigma-Delta Modulator Design for Wireless Standards. ICIT (2007)

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Publication Activity (10 Years)

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Jawar Singh