V. Bharath Sreenivasulu

Publication Activity (10 Years)

Years Active: 2021-2024
Publications (10 Years): 7

Top Topics

Quantitative Evaluation

Top Venues

Microelectron. J.

Publications

V. Bharath Sreenivasulu, Aruna Kumari Neelam, Asisa Kumar Panigrahy, Lokesh Vakkalakula, Jawar Singh, Shiv Govind Singh
Benchmarking of Multi-Bridge-Channel FETs Toward Analog and Mixed-Mode Circuit Applications. IEEE Access 12 (2024)
Aruna Kumari Neelam, V. Bharath Sreenivasulu, Vikas Vijayvargiya, Abhishek Kumar Upadhyay, J. Ajayan, M. Uma
Performance Comparison of Nanosheet FET, CombFET, and TreeFET: Device and Circuit Perspective. IEEE Access 12 (2024)
Asisa Kumar Panigrahy, Veera Venkata Sai Amudalapalli, Depuru Shobha Rani, Muralidhar Nayak Bhukya, Hima Bindu Valiveti, V. Bharath Sreenivasulu, Raghunandan Swain
Spacer Dielectric Analysis of Multi-Channel Nanosheet FET for Nanoscale Applications. IEEE Access 12 (2024)
V. Bharath Sreenivasulu, Aruna Kumari Neelam, Sekhar Reddy Kola, Jawar Singh, Yiming Li
Exploring the Performance of 3-D Nanosheet FET in Inversion and Junctionless Modes: Device and Circuit-Level Analysis and Comparison. IEEE Access 11 (2023)
B. Mounika, J. Ajayan, Sandip Bhattacharya, D. Nirmal, V. Bharath Sreenivasulu, N. Aruna Kumari
Investigation on effect of AlN barrier thickness and lateral scalability of Fe-doped recessed T-gate AlN/GaN/SiC HEMT with polarization-graded back barrier for future RF electronic applications. Microelectron. J. 140 (2023)
Aruru Sai Kumar, M. Deekshana, V. Bharath Sreenivasulu, Rajendra Prasad Somineni, D. Kanthi Sudha
Characterization for Sub-5nm Technology Nodes of Junctionless Gate-All-Around Nanowire FETs. ICCCNT (2022)
V. Bharath Sreenivasulu, Vadthiya Narendar
Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes. Microelectron. J. 116 (2021)