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Characterization for Sub-5nm Technology Nodes of Junctionless Gate-All-Around Nanowire FETs.

Aruru Sai KumarM. DeekshanaV. Bharath SreenivasuluRajendra Prasad SomineniD. Kanthi Sudha
Published in: ICCCNT (2022)
Keyphrases
  • nm technology
  • power consumption
  • low power
  • power dissipation
  • low cost
  • network structure
  • directed graph
  • shortest path
  • graph structure
  • minimum cost
  • hidden markov models
  • x ray