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Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes.
V. Bharath Sreenivasulu
Vadthiya Narendar
Published in:
Microelectron. J. (2021)
Keyphrases
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nm technology
power consumption
low power
optimization problems
global optimization
optimization algorithm
shortest path
high speed
optimization process
case study
low cost
network structure
optimization method
query language
multi objective
constrained optimization
objective function