Pseudo parallel architecture for AES with error correction.
Yi Xin SuJimson MathewJawar SinghDhiraj K. PradhanPublished in: SoCC (2008)
Keyphrases
- error correction
- parallel architecture
- parallel processing
- hardware implementation
- systolic array
- shared memory
- error detection
- error correcting
- data hiding
- distributed memory
- parallel implementation
- high level synthesis
- channel coding
- error detection and correction
- synthetic aperture sonar
- error control
- s box
- pattern recognition
- block codes
- encryption algorithm
- secret key
- distributed systems