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Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips.

Sam AmiriMohammad HosseinabadyAndrés RodríguezRafael AsenjoAngeles G. NavarroJosé L. Núñez-Yáñez
Published in: FPL (2018)
Keyphrases
  • high speed
  • level parallelism
  • response time
  • parallel processing
  • field programmable gate array
  • low cost
  • real time image processing
  • real time
  • shared memory
  • single chip