José L. Núñez-Yáñez

ORCID

Publication Activity (10 Years)

Years Active: 2003-2024
Publications (10 Years): 58

Top Venues

CoRR

ARC

Microprocess. Microsystems

J. Supercomput.

Publications

Olle Hansson, Mahdieh Grailoo, Oscar Gustafsson, José L. Núñez-Yáñez
Deep Quantization of Graph Neural Networks with Run-Time Hardware-Aware Training. ARC (2024)
Kaan Olgu, Tobias Kenter, José L. Núñez-Yáñez, Simon McIntosh-Smith
Optimisation and Evaluation of Breadth First Search with oneAPI/SYCL on Intel FPGAs: from Describing Algorithms to Describing Architectures. IWOCL (2024)
Habib Taha Kose, José L. Núñez-Yáñez, Robert J. Piechocki, James Pope
A Survey of Computationally Efficient Graph Neural Networks for Reconfigurable Systems. Inf. 15 (7) (2024)
Zichao Shen, José L. Núñez-Yáñez, Naim Dahnoun
Advanced Millimeter-Wave Radar System for Real-Time Multiple-Human Tracking and Fall Detection. Sensors 24 (11) (2024)
Zichao Shen, José L. Núñez-Yáñez, Naim Dahnoun
MMIDNet: Secure Human Identification Using Millimeter-wave Radar and Deep Learning. MECO (2024)
Kris Nikov, Kyriakos Georgiou, Zbigniew Chamski, Kerstin Eder, José L. Núñez-Yáñez
Accurate Energy Modelling on the Cortex-M0 Processor for Profiling and Static Analysis. CoRR (2023)
Simon Wegener, Kris K. Nikov, José L. Núñez-Yáñez, Kerstin Eder
EnergyAnalyzer: Using Static WCET Analysis Techniques to Estimate the Energy Consumption of Embedded Applications. CoRR (2023)
José L. Núñez-Yáñez, J. Andrés Otero, Eduardo de la Torre
Dynamically reconfigurable variable-precision sparse-dense matrix acceleration in Tensorflow Lite. Microprocess. Microsystems 98 (2023)
Zichao Shen, José L. Núñez-Yáñez, Naim Dahnoun
Multiple Human Tracking and Fall Detection Real-Time System Using Millimeter-Wave Radar and Data Fusion. MECO (2023)
José L. Núñez-Yáñez
Accelerating Graph Neural Networks in Pytorch with HLS and Deep Dataflows. ARC (2023)
Andrés Otero, Guillermo Sanllorente, Eduardo de la Torre, José L. Núñez-Yáñez
Evolutionary FPGA-Based Spiking Neural Networks for Continual Learning. ARC (2023)
Simon Wegener, Kris K. Nikov, José L. Núñez-Yáñez, Kerstin Eder
EnergyAnalyzer: Using Static WCET Analysis Techniques to Estimate the Energy Consumption of Embedded Applications. WCET (2023)
Kris Nikov, Kyriakos Georgiou, Zbigniew Chamski, Kerstin Eder, José L. Núñez-Yáñez
Accurate Energy Modelling on the Cortex-M0 Processor for Profiling and Static Analysis. ICECS 2022 (2022)
José L. Núñez-Yáñez
Fused Architecture for Dense and Sparse Matrix Processing in TensorFlow Lite. IEEE Micro 42 (6) (2022)
Kris Nikov, Marcos Martínez, Simon Wegener, José L. Núñez-Yáñez, Zbigniew Chamski, Kyriakos Georgiou, Kerstin Eder
Robust and Accurate Fine-Grain Power Models for Embedded Systems With No On-Chip PMU. IEEE Embed. Syst. Lett. 14 (3) (2022)
Andrés Rodríguez, Angeles G. Navarro, Kris Nikov, José L. Núñez-Yáñez, Ruben Gran, Darío Suárez Gracia, Rafael Asenjo
Lightweight asynchronous scheduling in heterogeneous reconfigurable systems. J. Syst. Archit. 124 (2022)
Kaan Olgu, Kris Nikov, José L. Núñez-Yáñez
Analysis of Graph Processing in Reconfigurable Devices for Edge Computing Applications. DSD (2022)
Zijie Wang, Jiajun Lu, José L. Núñez-Yáñez
A Low-complexity FPGA TDC based on a DSP Delay Line and a Wave Union Launcher. DSD (2022)
José L. Núñez-Yáñez, Neil J. Howard
Energy-efficient neural networks with near-threshold processors and hardware accelerators. J. Syst. Archit. 116 (2021)
Kris Nikov, Marcos Martinez, Simon Wegener, José L. Núñez-Yáñez, Zbigniew Chamski, Kyriakos Georgiou, Kerstin Eder
Robust and accurate fine-grain power models for embedded systems with no on-chip PMU. CoRR (2021)
José L. Núñez-Yáñez, Mohammad Hosseinabady
Sparse and dense matrix multiplication hardware for heterogeneous multi-precision neural networks. Array 12 (2021)
Krastin Nikov, José L. Núñez-Yáñez
Intra and inter-core power modelling for single-ISA heterogeneous processors. Int. J. Embed. Syst. 12 (3) (2020)
Mohammad Hosseinabady, José L. Núñez-Yáñez
Sparse Matrix-Dense Matrix Multiplication on Heterogeneous CPU+FPGA Embedded System. PARMA-DITAM@HiPEAC (2020)
Yang Zhang, Paul Hutchinson, Nicholas A. J. Lieven, José L. Núñez-Yáñez
Remaining Useful Life Estimation Using Long Short-Term Memory Neural Networks and Deep Fusion. IEEE Access 8 (2020)
José L. Núñez-Yáñez, Kris Nikov, Kerstin Eder, Mohammad Hosseinabady
Run-Time Power Modelling in Embedded GPUs with Dynamic Voltage and Frequency Scaling. PARMA-DITAM@HiPEAC (2020)
Andrés Rodríguez, Angeles G. Navarro, Rafael Asenjo, Francisco Corbera, Ruben Gran, Darío Suárez Gracia, José L. Núñez-Yáñez
Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform. J. Supercomput. 76 (6) (2020)
Kris Nikov, José L. Núñez-Yáñez, Matthew Horsnell
Evaluation of hybrid run-time power models for the ARM big.LITTLE architecture. CoRR (2020)
Demetrios A. M. Coutinho, Daniele De Sensi, Arthur Francisco Lorenzon, Kyriakos Georgiou, José L. Núñez-Yáñez, Kerstin Eder, Samuel Xavier de Souza
Performance and Energy Trade-Offs for Parallel Applications on Heterogeneous Multi-Processing Systems. CoRR (2020)
Kris Nikov, Mohammad Hosseinabady, Rafael Asenjo, Andrés Rodríguez, Angeles G. Navarro, José L. Núñez-Yáñez
High-Performance Simultaneous Multiprocessing for Heterogeneous System-on-Chip. CoRR (2020)
José L. Núñez-Yáñez, Kris Nikov, Kerstin Eder, Mohammad Hosseinabady
Run-Time Power Modelling in Embedded GPUs with Dynamic Voltage and Frequency Scaling. CoRR (2020)
Dave McEwan, José L. Núñez-Yáñez
Relationship Estimation Metrics for Binary SoC Data. LOD (2019)
Dave McEwan, Marcin Hlond, José L. Núñez-Yáñez
Visualizations for Understanding SoC Behaviour. PRIME (2019)
José L. Núñez-Yáñez, Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Darío Suárez Gracia, Ruben Gran
Simultaneous multiprocessing in a software-defined heterogeneous FPGA. J. Supercomput. 75 (8) (2019)
Andrés Rodríguez, Angeles G. Navarro, Rafael Asenjo, Francisco Corbera, Ruben Gran Tejero, Darío Suárez Gracia, José L. Núñez-Yáñez
Exploring heterogeneous scheduling for edge computing with CPU and FPGA MPSoCs. J. Syst. Archit. 98 (2019)
William Beasley, Brenda Gatusch, Daniel Connolly-Taylor, Chenyuan Teng, Asier Marzo, José L. Núñez-Yáñez
High-Performance Ultrasonic Levitation with FPGA-based Phased Arrays. CoRR (2019)
José L. Núñez-Yáñez, Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Darío Suárez Gracia, Ruben Gran
Correction to: Simultaneous multiprocessing in a software-defined heterogeneous FPGA. J. Supercomput. 75 (8) (2019)
Mohammad Hosseinabady, Mohd Amiruddin Bin Zainol, José L. Núñez-Yáñez
Heterogeneous FPGA+GPU Embedded Systems: Challenges and Opportunities. CoRR (2019)
José L. Núñez-Yáñez
Energy Proportional Neural Network Inference with Adaptive Voltage and Frequency Scaling. IEEE Trans. Computers 68 (5) (2019)
William Beasley, Brenda Gatusch, Daniel Connolly-Taylor, Chenyuan Teng, Asier Marzo, José L. Núñez-Yáñez
Ultrasonic Levitation with Software-Defined FPGAs and Electronically Phased Arrays. AHS (2019)
Dave McEwan, José L. Núñez-Yáñez
Relationship Detection Measures for Binary SoC Data. CoRR (2019)
Demetrios A. M. Coutinho, Kyriakos Georgiou, Kerstin I. Eder, José L. Núñez-Yáñez, Samuel Xavier de Souza
Performance and Energy Efficiency Trade-Offs in Single-ISA Heterogeneous Multi-Processing for Parallel Applications. VLSI-SoC (2019)
José L. Núñez-Yáñez
Energy Proportional Heterogenous Computing with Reconfigurable MPSoC. HPCS (2019)
Qianqiao Chen, Vaibhawa Mishra, José L. Núñez-Yáñez, Georgios Zervas
Reconfigurable Network Stream Processing on Virtualized FPGA Resources. Int. J. Reconfigurable Comput. 2018 (2018)
Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, José L. Núñez-Yáñez
Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips. FPL (2018)
Sam Amiri, Mohammad Hosseinabady, Simon McIntosh-Smith, José L. Núñez-Yáñez
Multi-precision convolutional neural networks on heterogeneous hardware. DATE (2018)
José L. Núñez-Yáñez, Mohammad Hosseinabady, Moslem Amiri, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Ruben Gran Tejero, Darío Suárez Gracia
Parallelizing Workload Execution in Embedded and High-Performance Heterogeneous Systems. CoRR (2018)
Qianqiao Chen, Vaibhawa Mishra, José L. Núñez-Yáñez, Georgios Zervas
Synchronizing reconfiguration of coherent functions on disaggregated FPGA resources. ReConFig (2017)
Felipe Galindo Sanchez, José L. Núñez-Yáñez
Energy proportional streaming spiking neural network in a reconfigurable system. Microprocess. Microsystems 53 (2017)
José L. Núñez-Yáñez, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Ruben Gran Tejero, Darío Suárez Gracia
Simultaneous Multiprocessing on a FPGA+CPU Heterogeneous System-On-Chip. PARCO (2017)
Yang Zhang, Paul Hutchinson, Nicholas A. J. Lieven, José L. Núñez-Yáñez
Optimal compression of vibration data with lifting wavelet transform and context-based arithmetic coding. EUSIPCO (2017)
José L. Núñez-Yáñez
Adaptive voltage scaling in a heterogeneous FPGA device with memory and logic in-situ detectors. Microprocess. Microsystems 51 (2017)
José L. Núñez-Yáñez, Tom Sun
Energy Efficient Video Fusion with Heterogeneous CPU-FPGA Devices. CoRR (2016)
Peng Sun, Alin Achim, Ian Hasler, Paul R. Hill, José L. Núñez-Yáñez
Energy efficient video fusion with heterogeneous CPU-FPGA devices. DATE (2016)
Nuno Roma, José L. Núñez-Yáñez
Editorial to special issue on energy efficient architectures for embedded systems. EURASIP J. Embed. Syst. 2016 (2016)
José L. Núñez-Yáñez
Computing to the Limit with Heterogeneous CPU-FPGA Devices in a Video Fusion Application. ARC (2016)
Krastin Nikov, José L. Núñez-Yáñez, Matthew Horsnell
Evaluation of Hybrid Run-Time Power Models for the ARM Big.LITTLE Architecture. EUC (2015)
Rafael Asenjo, Angeles G. Navarro, Andrés Rodríguez, José L. Núñez-Yáñez
Workload distribution and balancing in FPGAs and CPUs with OpenCL and TBB. PARCO (2015)
José L. Núñez-Yáñez, J. M. Moreno, Dimitrios S. Nikolopoulos
Guest Editorial. IET Comput. Digit. Tech. 9 (1) (2015)
José L. Núñez-Yáñez, Arash Beldachi
Run-time power and performance scaling with CPU-FPGA hybrids. AHS (2014)
Jin Chen, José L. Núñez-Yáñez, Alin Achim
Joint video fusion and super resolution based on Markov random fields. ICIP (2014)
Yun Wu, José L. Núñez-Yáñez, Roger F. Woods, Dimitrios S. Nikolopoulos
Power modelling and capping for heterogeneous ARM/FPGA SoCs. FPT (2014)
José L. Núñez-Yáñez
Energy efficient Reconfigurable Computing with Adaptive Voltage and Logic scaling. SIGARCH Comput. Archit. News 42 (4) (2014)
Peng Sun, José L. Núñez-Yáñez
Optimizing Memory Power in Hybrid ARM-FPGA Chips With Lossless Data Compression. FPGAworld (2014)
Arash Beldachi, José L. Núñez-Yáñez
Run-time power and performance scaling in 28 nm FPGAs. IET Comput. Digit. Tech. 8 (4) (2014)
Arash Beldachi, Simon J. Hollis, José L. Núñez-Yáñez
eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip. IET Comput. Digit. Tech. 8 (3) (2014)
Arash Farhadi Beldachi, José L. Núñez-Yáñez
Accurate power control and monitoring in ZYNQ boards. FPL (2014)
José L. Núñez-Yáñez, Geza Lore
Enabling accurate modeling of power and energy consumption in an ARM-based System-on-Chip. Microprocess. Microsystems 37 (3) (2013)
José L. Núñez-Yáñez
Energy proportional computing in commercial FPGAs with adaptive voltage scaling. FPGAworld (2013)
Jin Chen, José L. Núñez-Yáñez, Alin Achim
Video super-resolution using low rank matrix completion. ICIP (2013)
Jin Chen, José L. Núñez-Yáñez, Alin Achim
Approximate alpha-stable Markov Random Fields for video super-resolution. EUSIPCO (2012)
Jin Chen, José L. Núñez-Yáñez, Alin Achim
Video Super-Resolution Using Generalized Gaussian Markov Random Fields. IEEE Signal Process. Lett. 19 (2) (2012)
José L. Núñez-Yáñez, Arash Beldachi, Atukem Nabina, Mohammad Hosseinabady
Exploring dynamically reconfigurable multicore designs with NoRC designer. HPCS (2012)
José L. Núñez-Yáñez, Trevor Spiteri, George Vafiadis
Multi-standard reconfigurable motion estimation processor for hybrid video codecs. IET Comput. Digit. Tech. 5 (2) (2011)
Atukem Nabina, José L. Núñez-Yáñez
Dynamic Reconfiguration Optimisation with Streaming Data Decompression. FPL (2010)
Mohammad Hosseinabady, José L. Núñez-Yáñez
SystemC Architectural Transaction Level Modelling for Large NoCs. FDL (2010)
Mohammad Hosseinabady, José L. Núñez-Yáñez
Effective modelling of large NoCs using SystemC. ISCAS (2010)
José L. Núñez-Yáñez, Mohammad Hosseinabady, Atukem Nabina, Izhar Zaidi
Energy optimization in a Network-on-Chip with dynamically reconfigurable processing nodes. CCA/ISIC (2009)
Xiaolin Chen, Nishan Canagarajah, José L. Núñez-Yáñez
Backward Adaptive Pixel-based Fast Predictive Motion Estimation. IEEE Signal Process. Lett. 16 (5) (2009)
Mohammad Hosseinabady, José L. Núñez-Yáñez
Run-time resource management in fault-tolerant network on reconfigurable chips. FPL (2009)
Yiwei Zhang, José L. Núñez-Yáñez, Joe McGeehan, Edward Regan, Stephen Kelly
A biophysically accurate floating point somatic neuroprocessor. FPL (2009)
Mohammad Hosseinabady, José L. Núñez-Yáñez
Fault-tolerant dynamically reconfigurable NoC-based SoC. ASAP (2008)
Xiaolin Chen, Cedric Nishan Canagarajah, Raffaele Vitulli, José L. Núñez-Yáñez
Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture. ARC (2008)
Izhar Zaidi, Atukem Nabina, Cedric Nishan Canagarajah, José L. Núñez-Yáñez
Power/Area Analysis of a FPGA-Based Open-Source Processor using Partial Dynamic Reconfiguration. DSD (2008)
Vassilios A. Chouliaras, Vincent M. Dwyer, Shahrukh Agha, José L. Núñez-Yáñez, Dionysios I. Reisis, Konstantinos Nakos, Konstantinos Manolopoulos
Customization of an embedded RISC CPU with SIMD extensions for video encoding: A case study. Integr. 41 (1) (2008)
José L. Núñez-Yáñez, Doug A. Edwards, Antonio Marcello Coppola
Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems. IET Comput. Digit. Tech. 2 (3) (2008)
Izhar Zaidi, Atukem Nabina, Cedric Nishan Canagarajah, José L. Núñez-Yáñez
Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor. FPL (2008)
Xiaofeng Wu, Vassilios A. Chouliaras, José L. Núñez-Yáñez, Roger M. Goodall
A Novel Delta Sigma Control System Processor and Its VLSI Implementation. IEEE Trans. Very Large Scale Integr. Syst. 16 (3) (2008)
José L. Núñez-Yáñez, Vassilios A. Chouliaras, Jiri Gaisler
Dynamic Voltage Scaling in a FPGA-based System-on-Chip. FPL (2007)
R. Stapenhurst, Koushik Maharatna, Jimson Mathew, José L. Núñez-Yáñez, Dhiraj K. Pradhan
On the Hardware Reduction of z-Datapath of Vectoring CORDIC. ISCAS (2007)
José L. Núñez-Yáñez, Vassilios A. Chouliaras, Daniele Alfonso, Fabrizio S. Rovati
Hardware assisted rate distortion optimization with embedded CABAC accelerator for the H.264 advanced video codec. IEEE Trans. Consumer Electron. 52 (2) (2006)
Xiaofeng Wu, Vassilios A. Chouliaras, José L. Núñez-Yáñez, Roger Goodall, Tanya Vladimirova
A Novel Processor Architecture for Real-Time Control. Asia-Pacific Computer Systems Architecture Conference (2006)
José L. Núñez-Yáñez, Vassilios A. Chouliaras
High-performance arithmetic coding VLSI macro for the H264 video compression standard. IEEE Trans. Consumer Electron. 51 (1) (2005)
Vassilios A. Chouliaras, Tom R. Jacobs, Ashwin K. Kumaraswamy, José L. Núñez-Yáñez
Configurable Multiprocessors for High-Performance MPEG-4 Video Coding. ISVLSI (2005)
Tom R. Jacobs, José L. Núñez-Yáñez
A Thread and Data-Parallel MPEG-4 Video Encoder for a System-On-Chip Multiprocessor. ASAP (2005)
Konstantia Koutsomyti, S. R. Parr, Vassilios A. Chouliaras, José L. Núñez-Yáñez
Applying data-parallel and scalar optimizations for the efficient implementation of the G.729A and G.723.1 speech coding standards. SIP (2005)
Vassilios A. Chouliaras, José L. Núñez-Yáñez, David J. Mulvaney, Fabrizio S. Rovati, Daniele Alfonso
A multi-standard video accelerator based on a vector architecture. IEEE Trans. Consumer Electron. 51 (1) (2005)
José L. Núñez-Yáñez, Vassilios A. Chouliaras
A Configurable Statistical Lossless Compression Core Based on Variable Order Markov Modeling and Arithmetic Coding. IEEE Trans. Computers 54 (11) (2005)
José L. Núñez-Yáñez, Vassilios A. Chouliaras
Design and Implementation of a High-Performance and Silicon Efficient Arithmetic Coding Accelerator for the H.264 Advanced Video Codec. ASAP (2005)
E. G. Nikolova, David J. Mulvaney, Vassilios A. Chouliaras, José L. Núñez-Yáñez
A code compression scheme for improving SoC performance. SoC (2003)
Vassilios A. Chouliaras, José L. Núñez-Yáñez
Scalar coprocessors for accelerating the G723.1 and G729A speech coders. IEEE Trans. Consumer Electron. 49 (3) (2003)

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Publication Activity (10 Years)

Top Topics

Top Venues

José L. Núñez-Yáñez