Vassilios A. Chouliaras

Publication Activity (10 Years)

Years Active: 2003-2018
Publications (10 Years): 5

Top Venues

Microprocess. Microsystems

Microelectron. J.

J. Syst. Archit.

Microelectron. Reliab.

Loughborough University, UK (PHD)

Education History

Loughborough University, UK

PHD

Publications

Jianjia Ma, Eef Hogervorst, Daniele Magistro, Vassilios A. Chouliaras, Massimiliano Zecca
Development of Sensorised Resistance Band for Objective Exercise Measurement: Activities Classification Trial. EMBC (2018)
Partheepan Kandaswamy, James A. Flint, Vassilios A. Chouliaras
Shape reconstruction using instruction systolic array. IEEE SENSORS (2017)
Konstantinos Manolopoulos, Dionisios I. Reisis, Vassilios A. Chouliaras
An efficient multiple precision floating-point Multiply-Add Fused unit. Microelectron. J. 49 (2016)
Vassilios A. Chouliaras, David Stevens, Vincent M. Dwyer
VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads. Microprocess. Microsystems 47 (2016)
Samuel J. Parker, Vassilios A. Chouliaras
An OpenCL software compilation framework targeting an SoC-FPGA VLIW chip multiprocessor. J. Syst. Archit. 68 (2016)
M. K. Lim, Vassilios A. Chouliaras, Chee Lip Gan, Vincent M. Dwyer
Bidirectional electromigration failure. Microelectron. Reliab. 53 (9-11) (2013)
Yimin Zhou, Ludovic A. Krundel, David J. Mulvaney, Vassilios A. Chouliaras, Guoqing Xu, Guoqiang Fu
Autonomous learning design in system-on-chip. ROBIO (2013)
Vassilios A. Chouliaras, Konstantia Koutsomyti, Simon Parr, David J. Mulvaney, Mark Milward
Architecture, performance modeling and VLSI implementation methodologies for ASIC vector processors: A case study in telephony workloads. Microprocess. Microsystems 37 (8-D) (2013)
Mark Milward, David Stevens, Vassilios A. Chouliaras
Embedded UML design flow to the configurable LE1 MultiCore VLIW processor. ReCoSoC (2012)
David Stevens, Vassilios A. Chouliaras, Vicente Azorin-Peris, Jia Zheng, Angelos Echiadis, Sijung Hu
BioThreads: A Novel VLIW-Based Chip Multiprocessor for Accelerating Biomedical Image Processing Applications. IEEE Trans. Biomed. Circuits Syst. 6 (3) (2012)
Vassilios A. Chouliaras, George Lentaris, Dionisios I. Reisis, David Stevens
Customizing a VLIW Chip Multiprocessor for Motion Estimation Algorithms. ARCS Workshops (2011)
Konstantinos Manolopoulos, Dionisios I. Reisis, Vassilios A. Chouliaras
An efficient multiple precision floating-point multiplier. ICECS (2011)
Konstantinos Babionitakis, Vassilios A. Chouliaras, Konstantinos Manolopoulos, Konstantinos Nakos, Dionysios I. Reisis, Nikolaos Vlassopoulos
Fully Systolic FFT Architecture for Giga-sample Applications. J. Signal Process. Syst. 58 (3) (2010)
Konstantinos Manolopoulos, Dionysios I. Reisis, Vassilios A. Chouliaras
An efficient dual-mode floating-point Multiply-Add Fused Unit. ICECS (2010)
David Stevens, Vassilios A. Chouliaras
LE1: A Parameterizable VLIW Chip-Multiprocessor with Hardware PThreads Support. ISVLSI (2010)
Ludovic A. Krundel, David J. Mulvaney, Vassilios A. Chouliaras
Autonomous Design in VLSI: An In-House Universal Cellular Neural Platform. ISVLSI (2010)
Ludovic A. Krundel, David J. Mulvaney, Vassilios A. Chouliaras
Autonomous Design in VLSI: Growing and Learning on Silicon. ISVLSI (2010)
David Stevens, Nick Glynn, Panagiotis Galiatsatos, Vassilios A. Chouliaras, Dionysios I. Reisis
Evaluating the performance of a configurable, extensible VLIW processor in FFT execution. ICECS (2009)
Vassilios A. Chouliaras, Panagiotis Galiatsatos, Konstantinos Nakos, Dionysios I. Reisis, Nikolaos Vlassopoulos
Efficient cascaded VLSI FFT architecture for OFDM systems. ICECS (2009)
Vassilios A. Chouliaras, Konstantinos Manolopoulos, Dionysios I. Reisis
A configurable length, Fused Multiply-Add floating point unit for a VLIW processor. SoCC (2009)
José Luis Núñez-Yáñez, Eddie Hung, Vassilios A. Chouliaras
A configurable and programmable motion estimation processor for the H.264 video codec. FPL (2008)
Vassilios A. Chouliaras, Vincent M. Dwyer, Shahrukh Agha, José L. Núñez-Yáñez, Dionysios I. Reisis, Konstantinos Nakos, Konstantinos Manolopoulos
Customization of an embedded RISC CPU with SIMD extensions for video encoding: A case study. Integr. 41 (1) (2008)
Jia Zheng, Sijung Hu, Vassilios A. Chouliaras, Ron Summers
Feasibility of Imaging Photoplethysmography. BMEI (2) (2008)
Xiaofeng Wu, Vassilios A. Chouliaras, José L. Núñez-Yáñez, Roger M. Goodall
A Novel Delta Sigma Control System Processor and Its VLSI Implementation. IEEE Trans. Very Large Scale Integr. Syst. 16 (3) (2008)
Emmanuel Touloupis, James A. Flint, Vassilios A. Chouliaras, David D. Ward
Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor. IEEE Trans. Computers 56 (12) (2007)
Konstantinos Manolopoulos, Konstantinos Nakos, Dionysios I. Reisis, Nikolaos Vlassopoulos, Vassilios A. Chouliaras
High Performance 16K, 64K, 256K complex points VLSI Systolic FFT Architectures. ICECS (2007)
José L. Núñez-Yáñez, Vassilios A. Chouliaras, Jiri Gaisler
Dynamic Voltage Scaling in a FPGA-based System-on-Chip. FPL (2007)
Zhenhuan Zhu, David J. Mulvaney, Vassilios A. Chouliaras
Hardware implementation of a novel genetic algorithm. Neurocomputing 71 (1-3) (2007)
Vassilios A. Chouliaras, James A. Flint, Yibin Li
A Transmission Line Modelling VLSI processor designed with a novel Electronic System Level Methodology. ICECS (2007)
Tom R. Jacobs, Vassilios A. Chouliaras, David J. Mulvaney
Thread-parallel MPEG-2, MPEG-4 and H.264 video encoders for SoC multi-processor architectures. IEEE Trans. Consumer Electron. 52 (1) (2006)
Vassilios A. Chouliaras, Konstantia Koutsomyti, Tom R. Jacobs, Simon Parr, David J. Mulvaney, Robert Thomson
SystemC-defined SIMD instructions for high performance SoC architectures. ICECS (2006)
José L. Núñez-Yáñez, Vassilios A. Chouliaras, Daniele Alfonso, Fabrizio S. Rovati
Hardware assisted rate distortion optimization with embedded CABAC accelerator for the H.264 advanced video codec. IEEE Trans. Consumer Electron. 52 (2) (2006)
Xiaofeng Wu, Vassilios A. Chouliaras, José L. Núñez-Yáñez, Roger Goodall, Tanya Vladimirova
A Novel Processor Architecture for Real-Time Control. Asia-Pacific Computer Systems Architecture Conference (2006)
Zhenhuan Zhu, David J. Mulvaney, Vassilios A. Chouliaras
Investigation Of A New Genetic Algorithm Designed For System-On-Chip Realization. IEEE Congress on Evolutionary Computation (2006)
Konstantinos Babionitakis, Konstantinos Manolopoulos, Konstantinos Nakos, Dionysios I. Reisis, Nikolaos Vlassopoulos, Vassilios A. Chouliaras
A High Performance VLSI FFT Architecture. ICECS (2006)
José L. Núñez-Yáñez, Vassilios A. Chouliaras
High-performance arithmetic coding VLSI macro for the H264 video compression standard. IEEE Trans. Consumer Electron. 51 (1) (2005)
Vincent M. Dwyer, Shahrukh Agha, Vassilios A. Chouliaras
Reduced-Bit, Full Search Block-Matching Algorithms and Their Hardware Realizations. ACIVS (2005)
Vassilios A. Chouliaras, Tom R. Jacobs, Ashwin K. Kumaraswamy, José L. Núñez-Yáñez
Configurable Multiprocessors for High-Performance MPEG-4 Video Coding. ISVLSI (2005)
Vassilios A. Chouliaras, Vincent M. Dwyer, Shahrukh Agha
On the Performance Improvement of Sub-sampling MPEG-2 Motion Estimation Algorithms with Vector/SIMD Architectures. ACIVS (2005)
Konstantia Koutsomyti, S. R. Parr, Vassilios A. Chouliaras, José L. Núñez-Yáñez
Applying data-parallel and scalar optimizations for the efficient implementation of the G.729A and G.723.1 speech coding standards. SIP (2005)
Vassilios A. Chouliaras, José L. Núñez-Yáñez, David J. Mulvaney, Fabrizio S. Rovati, Daniele Alfonso
A multi-standard video accelerator based on a vector architecture. IEEE Trans. Consumer Electron. 51 (1) (2005)
José L. Núñez-Yáñez, Vassilios A. Chouliaras
A Configurable Statistical Lossless Compression Core Based on Variable Order Markov Modeling and Arithmetic Coding. IEEE Trans. Computers 54 (11) (2005)
José L. Núñez-Yáñez, Vassilios A. Chouliaras
Design and Implementation of a High-Performance and Silicon Efficient Arithmetic Coding Accelerator for the H.264 Advanced Video Codec. ASAP (2005)
Christos Grecos, Azilah Saparon, Vassilios A. Chouliaras
Three novel low complexity scanning orders for MPEG-2 full search motion estimation. Real Time Imaging 10 (1) (2004)
Xiaofeng Wu, Vassilios A. Chouliaras, Roger Goodall
An application-specific processor hard macro for real-time control. SoCC (2004)
E. G. Nikolova, David J. Mulvaney, Vassilios A. Chouliaras, José L. Núñez-Yáñez
A code compression scheme for improving SoC performance. SoC (2003)
Vassilios A. Chouliaras, José L. Núñez-Yáñez
Scalar coprocessors for accelerating the G723.1 and G729A speech coders. IEEE Trans. Consumer Electron. 49 (3) (2003)

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Publication Activity (10 Years)

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Vassilios A. Chouliaras