Eduardo de la Torre

Publication Activity (10 Years)

Years Active: 1993-2024
Publications (10 Years): 46

Top Topics

Hardware Architecture

Highly Flexible

Inverse Kinematics

Top Venues

Microprocess. Microsystems

Publications

Juan Encinas, Alfonso Rodríguez, Andrés Otero, Eduardo de la Torre
Data-driven modeling of reconfigurable multi-accelerator systems under dynamic workloads. Microprocess. Microsystems 107 (2024)
José Núñez-Yáñez, Andrés Otero, Eduardo de la Torre
Dynamically Reconfigurable Variable-precision Sparse-Dense Matrix Acceleration in Tensorflow Lite. CoRR (2023)
José L. Núñez-Yáñez, J. Andrés Otero, Eduardo de la Torre
Dynamically reconfigurable variable-precision sparse-dense matrix acceleration in Tensorflow Lite. Microprocess. Microsystems 98 (2023)
Andrés Otero, Guillermo Sanllorente, Eduardo de la Torre, José L. Núñez-Yáñez
Evolutionary FPGA-Based Spiking Neural Networks for Continual Learning. ARC (2023)
Rafael Zamacola, Andrés Otero, Alfonso Rodríguez, Eduardo de la Torre
Just-In-Time Composition of Reconfigurable Overlays (Invited Talk). PARMA-DITAM@HiPEAC (2022)
Alfonso Rodríguez, Andrés Otero, Marco Platzner, Eduardo de la Torre
Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs. IEEE Trans. Computers 71 (11) (2022)
Daniel Vázquez, Alfonso Rodríguez, Andrés Otero, Eduardo de la Torre
Extending RISC-V Processor Datapaths with Multi-Grain Reconfigurable Overlays. DCIS (2022)
Javier Laserna, Andrés Otero, Eduardo de la Torre
A Multi-FPGA Scalable Framework for Deep Reinforcement Learning Through Neuroevolution. ARC (2022)
Juan Encinas, Alfonso Rodríguez, Andrés Otero, Eduardo de la Torre
Run-Time Monitoring and ML-Based Modeling in Reconfigurable Multi-Accelerator Systems. DCIS (2021)
Rafael Zamacola, Andrés Otero, Eduardo de la Torre
Multi-grain reconfigurable and scalable overlays for hardware accelerator composition. J. Syst. Archit. 121 (2021)
Rodrigo Marino, Cristian Wisultschew, Andrés Otero, José Manuel Lanza-Gutiérrez, Jorge Portilla, Eduardo de la Torre
A Machine-Learning-Based Distributed System for Fault Diagnosis With Scalable Detection Quality in Industrial IoT. IEEE Internet Things J. 8 (6) (2021)
Leonardo Suriano, Andrés Otero, Alfonso Rodríguez, Manuel Sánchez-Renedo, Eduardo de la Torre
Exploiting Multi-Level Parallelism for Run-Time Adaptive Inverse Kinematics on Heterogeneous MPSoCs. IEEE Access 8 (2020)
Leonardo Suriano, David Lima, Eduardo de la Torre
Accelerating a Classic 3D Video Game on Heterogeneous Reconfigurable MPSoCs. ARC (2020)
Arturo Perez, Alfonso Rodríguez, Andrés Otero, David González Arjona, Álvaro Jiménez-Peralo, Miguel Ángel Verdugo, Eduardo de la Torre
Run-Time Reconfigurable MPSoC-Based On-Board Processor for Vision-Based Space Navigation. IEEE Access 8 (2020)
Alberto García Ortiz, Rafael Zamacola, Alfonso Rodríguez, Andrés Otero, Eduardo de la Torre
Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-accelerator Systems. ARC (2020)
Rafael Zamacola, Andrés Otero, Alberto García-Martínez, Eduardo de la Torre
An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems. IEEE Access 8 (2020)
Alberto García Ortiz, Alfonso Rodríguez, Andrés Otero, Eduardo de la Torre
Data Transfer Modeling and Optimization in Reconfigurable Multi-Accelerator Systems. ReCoSoC (2019)
Luca Fanni, Leonardo Suriano, Claudio Rubattu, Pablo Sánchez, Eduardo de la Torre, Francesca Palumbo
A Dataflow Implementation of Inverse Kinematics on Reconfigurable Heterogeneous MPSoC. CPS Summer School, PhD Workshop (2019)
Francesca Palumbo, Tiziana Fanni, Carlo Sau, Alfonso Rodríguez, Daniel Madroñal, Karol Desnos, Antoine Morvan, Maxime Pelcat, Claudio Rubattu, Raquel Lazcano, Luigi Raffo, Eduardo de la Torre, Eduardo Juárez, César Sanz, Pablo Sanchez de Rojas
Hardware/Software Self-adaptation in CPS: The CERBERO Project Approach. SAMOS (2019)
Alfonso Rodríguez, Lucana Santos, Roberto Sarmiento, Eduardo de la Torre
Scalable Hardware-Based On-Board Processing for Run-Time Adaptive Lossless Hyperspectral Compression. IEEE Access 7 (2019)
Leonardo Suriano, Florian Arrestier, Alfonso Rodríguez, Julien Heulot, Karol Desnos, Maxime Pelcat, Eduardo de la Torre
DAMHSE: Programming heterogeneous MPSoCs with hardware acceleration using dataflow-based design space exploration and automated rapid prototyping. Microprocess. Microsystems 71 (2019)
Cristian Wisultschew, Andrés Otero, Jorge Portilla, Eduardo de la Torre
Artificial Vision on Edge IoT Devices: A Practical Case for 3D Data Classification. DCIS (2019)
Javier Mora, Rubén Salvador, Eduardo de la Torre
On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming. Genet. Program. Evolvable Mach. 20 (2) (2019)
Rodrigo Marino, Sergio Quintero, José Manuel Lanza-Gutiérrez, Teresa Riesgo, Miguel Holgado, Jorge Portilla, Eduardo de la Torre
Hardware Accelerator for Ethanol Detection in Water Media based on Machine Learning Techniques. DCIS (2019)
Rafael Zamacola, Alberto García-Martínez, Javier Mora, Andrés Otero, Eduardo de la Torre
Automated Tool and Runtime Support for Fine-Grain Reconfiguration in Highly Flexible Reconfigurable Systems. FCCM (2019)
Arturo Perez, Andrés Otero, Eduardo de la Torre
Performance Analysis of SEE Mitigation Techniques on Zynq Ultrascale + Hardened Processing Fabrics. AHS (2018)
Alfonso Rodríguez, Juan Valverde, Jorge Portilla, Andrés Otero, Teresa Riesgo, Eduardo de la Torre
Framework. Sensors 18 (6) (2018)
Alberto García Ortiz, Alfonso Rodríguez, Raúl Guerra, Sebastián López, Andrés Otero, Roberto Sarmiento, Eduardo de la Torre
A Runtime-Scalable and Hardware-Accelerated Approach to On-Board Linear Unmixing of Hyperspectral Images. Remote. Sens. 10 (11) (2018)
Rafael Zamacola, Alberto García-Martínez, Javier Mora, Andrés Otero, Eduardo de la Torre
IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado. ReConFig (2018)
Javier Mora, Eduardo de la Torre
Accelerating the evolution of a systolic array-based evolvable hardware system. Microprocess. Microsystems 56 (2018)
Leonardo Suriano, Daniel Madroñal, Alfonso Rodríguez, Eduardo Juárez, César Sanz, Eduardo de la Torre
A Unified Hardware/Software Monitoring Method for Reconfigurable Computing Architectures Using PAPI. ReCoSoC (2018)
Tiziana Fanni, Alfonso Rodríguez, Carlo Sau, Leonardo Suriano, Francesca Palumbo, Luigi Raffo, Eduardo de la Torre
Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical Systems. ReConFig (2018)
Leonardo Suriano, Alfonso Rodríguez, Karol Desnos, Maxime Pelcat, Eduardo de la Torre
Analysis of a heterogeneous multi-core, multi-hw-accelerator-based system designed using PREESM and SDSoC. ReCoSoC (2017)
Michael Masin, Francesca Palumbo, Hans Myrhaug, J. A. de Oliveira Filho, M. Pastena, Maxime Pelcat, Luigi Raffo, Francesco Regazzoni, A. A. Sanchez, Antonella Toffetti, Eduardo de la Torre, Katiuscia Zedda
Cross-layer design of reconfigurable cyber-physical systems. DATE (2017)
Arturo Perez, Leonardo Suriano, Andrés Otero, Eduardo de la Torre
Dynamic reconfiguration under RTEMS for fault mitigation and functional adaptation in SRAM-based SoPCs for space systems. AHS (2017)
Teresa Cervero, Andrés Otero, Sebastián López, Eduardo de la Torre, Gustavo Marrero Callicó, Teresa Riesgo, Roberto Sarmiento
A scalable H.264/AVC deblocking filter architecture. J. Real Time Image Process. 12 (1) (2016)
René Cumplido, Peter Athanas, Eduardo de la Torre
Introduction to the Special Section on FPGAs Technology and Applications. Comput. Electr. Eng. 49 (2016)
Eduardo de la Torre, Jorge Portilla, Teresa Riesgo
Letter from the guest editors of the special issue on DCIS 2014. Microprocess. Microsystems 39 (8) (2015)
René Cumplido, Eduardo de la Torre, Claudia Feregrino Uribe, Michael J. Wirthlin
Introduction to Special issue on Reconfigurable computing and FPGAs. Microprocess. Microsystems 39 (7) (2015)
Alfonso Rodríguez, Juan Valverde, Cesar Castanares, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo
Live demonstration: A dynamically adaptable image processing application running in an FPGA-based WSN platform. ISCAS (2015)
Wei He, Shivam Bhasin, Andrés Otero, Tarik Graba, Eduardo de la Torre, Jean-Luc Danger
Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis. IET Inf. Secur. 9 (1) (2015)
Filip Veljkovic, Teresa Riesgo, Eduardo de la Torre
Adaptive reconfigurable voting for enhanced reliability in medium-grained fault tolerant architectures. AHS (2015)
Alfonso Rodríguez, Juan Valverde, Cesar Castanares, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo
Execution modeling in self-aware FPGA-based architectures for efficient resource management. ReCoSoC (2015)
Alberto García Ortiz, Daniel Gregorek, Eduardo de la Torre, Juha Plosila
Message from the chairs. ReCoSoC (2015)
Javier Mora, Andrés Otero, Eduardo de la Torre, Teresa Riesgo
Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs. ReCoSoC (2015)
Alfonso Rodríguez, Juan Valverde, Eduardo de la Torre
Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs. ReConFig (2015)
Alfonso Rodríguez, Juan Valverde, Eduardo de la Torre, Teresa Riesgo
Dynamic management of multikernel multithread accelerators using Dynamic Partial Reconfiguration. ReCoSoC (2014)
Chenyang Tu, Wei He, Neng Gao, Eduardo de la Torre, Zeyi Liu, Limin Liu
A Progressive Dual-Rail Routing Repair Approach for FPGA Implementation of Crypto Algorithm. ISPEC (2014)
Blanca Lopez, Juan Valverde, Eduardo de la Torre, Teresa Riesgo
Power-aware multi-objective evolvable hardware system on an FPGA. AHS (2014)
Wei He, Andrés Otero, Eduardo de la Torre, Teresa Riesgo
Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic. Microprocess. Microsystems 38 (8) (2014)
Peter M. Athanas, René Cumplido, Claudia Feregrino Uribe, Eduardo de la Torre
Introduction to Special issue on FPGA Devices and Applications. Microprocess. Microsystems 38 (8) (2014)
Peter Athanas, René Cumplido, Eduardo de la Torre
Introduction to the special issue on FPGA Technology and Applications. Comput. Electr. Eng. 40 (4) (2014)
Filip Veljkovic, Teresa Riesgo, Eduardo de la Torre, Raul Regada, Luis Berrojo
A run time adaptive architecture to trade-off performance for fault tolerance applied to a DVB on-board processor. AHS (2014)
Juan Valverde, Alfonso Rodríguez, Julio Camarero, Andrés Otero, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo
A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems. FPL (2014)
Angel Gallego, Javier Mora, Andrés Otero, Eduardo de la Torre, Teresa Riesgo
A scalable evolvable hardware processing array. ReConFig (2013)
Angel Gallego, Javier Mora, Andrés Otero, Blanca Lopez, Eduardo de la Torre, Teresa Riesgo
A self-adaptive image processing application based on evolvable and scalable hardware. FPL (2013)
Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina
Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing. IEEE Trans. Computers 62 (8) (2013)
Javier Mora, Angel Gallego, Andrés Otero, Eduardo de la Torre, Teresa Riesgo
Noise-agnostic adaptive image filtering without training references on an evolvable hardware platform. DASIP (2013)
Javier Mora, Angel Gallego, Andrés Otero, Blanca Lopez, Eduardo de la Torre, Teresa Riesgo
A noise-agnostic self-adaptive image processing application based on evolvable hardware. DASIP (2013)
Angel Gallego, Javier Mora, Andrés Otero, Rubén Salvador, Eduardo de la Torre, Teresa Riesgo
A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays. IPDPS Workshops (2013)
Iakovos Mavroidis, Ioannis Mavroidis, Ioannis Papaefstathiou, Luciano Lavagno, Mihai T. Lazarescu, Eduardo de la Torre, Florian Schäfer
FASTCUDA: Open Source FPGA Accelerator & Hardware-Software Codesign Toolset for CUDA Kernels. DSD (2012)
Wei He, Eduardo de la Torre, Teresa Riesgo
An Interleaved EPE-Immune PA-DPL Structure for Resisting Concentrated EM Side Channel Attacks on FPGA Implementation. COSADE (2012)
Wei He, Andrés Otero, Eduardo de la Torre, Teresa Riesgo
Automatic generation of identical routing pairs for FPGA implemented DPL logic. ReConFig (2012)
Miguel Lombardo, Julio Camarero, Juan Valverde, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo
Power management techniques in an FPGA-based WSN node for high performance applications. ReCoSoC (2012)
Andrés Otero, Eduardo de la Torre, Teresa Riesgo
Dreams: A tool for the design of dynamically reconfigurable embedded and modular systems. ReConFig (2012)
Juan Valverde, Andrés Otero, Miguel Lopez, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo
Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks. Sensors 12 (3) (2012)
Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina
Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration. FPL (2012)
Andrés Otero, Rubén Salvador, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina
A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems. AHS (2011)
Wei He, Eduardo de la Torre, Teresa Riesgo
A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations. ReConFig (2011)
Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Teresa Cervero, Sebastián López, Gustavo Marrero Callicó, Roberto Sarmiento
Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs. FPL (2011)
Teresa Cervero, Andrés Otero, Sebastián López, Eduardo de la Torre, Gustavo Marrero Callicó, Roberto Sarmiento, Teresa Riesgo
A novel scalable Deblocking Filter architecture for H.264/AVC and SVC video codecs. ICME (2011)
Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina
Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support. AHS (2011)
Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Lukás Sekanina, Teresa Riesgo
Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems. ReConFig (2011)
Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo
Reconfigurable Networks on Chip: DRNoC architecture. J. Syst. Archit. 56 (7) (2010)
Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Yana Esteves Krasteva
Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs. FPL (2010)
Andrés Otero, Angel Morales-Cas, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo
A Modular Peripheral to Support Self-Reconfiguration in SoCs. DSD (2010)
Andrés Otero, Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo
Generic Systolic Array for Run-Time Scalable Cores. ARC (2010)
Jorge Portilla, Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Oliver Stecklina, Steffen Peter, Peter Langendörfer
Adaptable Security in Wireless Sensor Networks by Using Reconfigurable ECC Hardware Coprocessors. Int. J. Distributed Sens. Networks 6 (1) (2010)
Yana Esteves Krasteva, Francisco Criado, Eduardo de la Torre, Teresa Riesgo
A Fast Emulation-Based NoC Prototyping Framework. ReConFig (2008)
Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo
Reconfigurable Heterogeneous Communications and Core Reallocation for Dynamic HW Task Management. ISCAS (2007)
Eduardo Peña, Eduardo de la Torre, Angel de Castro, Teresa Riesgo
A digital system to emulate wireless networks. IET Comput. Digit. Tech. 1 (5) (2007)
Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo
Partial Reconfiguration for Core Reallocation and Flexible Communications. ReCoSoC (2006)
Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo, Didier Joly
Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems. FPL (2006)
Jorge Portilla, Angel de Castro, Eduardo de la Torre, Teresa Riesgo
A Modular Architecture for Nodes in Wireless Sensor Networks. J. Univers. Comput. Sci. 12 (3) (2006)
Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo
Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs. IEEE International Workshop on Rapid System Prototyping (2005)
Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo
Flexible Core Reallocation for Virtex II Structures. ERSA (2005)
Mario García-Valderas, Eduardo de la Torre, F. Ariza, Teresa Riesgo
Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion. FPL (2004)
Eduardo de la Torre, Teresa Riesgo, Javier Uceda, E. Macip, M. Rizzi
Highly Configurable Control Boards: A Tool and a Design Experience. IEEE International Workshop on Rapid System Prototyping (2000)
Teresa Riesgo, Yago Torroja, Eduardo de la Torre
Design methodologies based on hardware description languages. IEEE Trans. Ind. Electron. 46 (1) (1999)
Teresa Riesgo, Yago Torroja, Eduardo de la Torre, Javier Uceda
Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models. DATE (1998)
Eduardo de la Torre, J. Calvo, Javier Uceda
Model generation of test logic for macrocell based designs. EURO-DAC (1996)
Maria José Aguado, Miguel Miranda, Eduardo de la Torre, Carlos A. López-Barrio
A dynamic communication strategy for the distributed ATPG system DPLATON. EURO-DAC (1993)
Maria José Aguado, Eduardo de la Torre, Miguel Miranda, Carlos A. López-Barrio
Distributed Implementation of an ATPG System Using Dynamic Fault Allocation. ITC (1993)