Tarik Graba

Publication Activity (10 Years)

Years Active: 2006-2023
Publications (10 Years): 15

Top Topics

Hardware Architecture

Stochastic Model

Top Venues

IEEE Trans. Computers

Publications

Guillaume Soudais, Tarik Graba, Yves Mathieu, Sébastien Bigo
Jitter Compensation Mechanism for Dynamic Deterministic Networks. OFC (2023)
Etienne Tehrani, Tarik Graba, Abdelmalek Si-Merabet, Jean-Luc Danger
RSM Protection of the PRESENT Lightweight Cipher as a RISC-V Extension. DSD (2021)
Ville Yli-Mäyry, Rei Ueno, Noriyuki Miura, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Naofumi Homma
Diffusional Side-Channel Leakage From Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE. IEEE Trans. Inf. Forensics Secur. 16 (2021)
Rei Ueno, Naofumi Homma, Sumio Morioka, Noriyuki Miura, Kohei Matsuda, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger
High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. IEEE Trans. Computers 69 (4) (2020)
Etienne Tehrani, Tarik Graba, Abdelmalek Si-Merabet, Jean-Luc Danger
RISC-V Extension for Lightweight Cryptography. DSD (2020)
Etienne Tehrani, Tarik Graba, Abdelmalek Si-Merabet, Sylvain Guilley, Jean-Luc Danger
Classification of Lightweight Block Ciphers for Specific Processor Accelerated Implementations. ICECS (2019)
Jean-Luc Danger, Risa Yashiro, Tarik Graba, Yves Mathieu, Abdelmalek Si-Merabet, Kazuo Sakiyama, Noriyuki Miura, Makoto Nagata
Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology. DSD (2018)
Etienne Tehrani, Jean-Luc Danger, Tarik Graba
Generic Architecture for Lightweight Block Ciphers: A First Step Towards Agile Implementation of Multiple Ciphers. WISTP (2018)
Laurent Sauvage, Tarik Graba, Thibault Porteboeuf
Multi-level formal verification - A new approach against fault injection attack. J. Cryptogr. Eng. 7 (1) (2017)
Xuan Thuy Ngo, Jean-Luc Danger, Sylvain Guilley, Tarik Graba, Yves Mathieu, Zakaria Najm, Shivam Bhasin
Cryptographically Secure Shield for Security IPs Protection. IEEE Trans. Computers 66 (2) (2017)
Sumanta Chaudhuri, Tarik Graba, Yves Mathieu
Multi-Valued Routing Tracks for FPGAs in 28nm FDSOI Technology. CoRR (2016)
Han Le Duc, Duc Minh Nguyen, Chadi Jabbour, Tarik Graba, Patricia Desgreys, Olivier Jamin, Van Tam Nguyen
All-Digital Calibration of Timing Skews for TIADCs Using the Polyphase Decomposition. IEEE Trans. Circuits Syst. II Express Briefs (1) (2016)
Han Le Duc, Duc Minh Nguyen, Chadi Jabbour, Tarik Graba, Patricia Desgreys, Olivier Jamin, Van Tam Nguyen
Hardware implementation of all digital calibration for undersampling TIADCs. ISCAS (2015)
Wei He, Shivam Bhasin, Andrés Otero, Tarik Graba, Eduardo de la Torre, Jean-Luc Danger
Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis. IET Inf. Secur. 9 (1) (2015)
Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger
Countering early propagation and routing imbalance of DPL designs in a tree-based FPGA. ICICDT (2015)
Shivam Bhasin, Tarik Graba, Jean-Luc Danger, Zakaria Najm
A look into SIMON from a side-channel perspective. HOST (2014)
Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Habib Mehrez
Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security. FPL (2014)
Taoufik Chouta, Tarik Graba, Jean-Luc Danger, Julien Bringer, Maël Berthier, Yves Bocktaels, Mélanie Favre, Hervé Chabanne
Side channel analysis on an embedded hardware fingerprint biometric comparator & low cost countermeasures. HASP@ISCA (2014)
Maël Berthier, Yves Bocktaels, Julien Bringer, Hervé Chabanne, Taoufik Chouta, Jean-Luc Danger, Mélanie Favre, Tarik Graba
Studying Leakages on an Embedded Biometric System Using Side Channel Analysis. COSADE (2014)
Maël Berthier, Yves Bocktaels, Julien Bringer, Hervé Chabanne, Taoufik Chouta, Jean-Luc Danger, Mélanie Favre, Tarik Graba
Studying Potential Side Channel Leakages on an Embedded Biometric Comparison System. IACR Cryptol. ePrint Arch. 2014 (2014)
Jean-Michel Cioranesco, Jean-Luc Danger, Tarik Graba, Sylvain Guilley, Yves Mathieu, David Naccache, Xuan Thuy Ngo
Cryptographically secure shields. HOST (2014)
Shivam Bhasin, Jean-Luc Danger, Tarik Graba, Yves Mathieu, Daisuke Fujimoto, Makoto Nagata
Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology. ES4CPS@DATE (2014)
Molka Ben-Romdhane, Tarik Graba, Jean-Luc Danger
Stochastic Model of a Metastability-Based True Random Number Generator. TRUST (2013)
Florent Lozach, Molka Ben-Romdhane, Tarik Graba, Jean-Luc Danger
FPGA Design of an Open-Loop True Random Number Generator. DSD (2013)
Molka Ben-Romdhane, Tarik Graba, Jean-Luc Danger, Yves Mathieu
Design methodology of an ASIC TRNG based on an open-loop delay chain. NEWCAS (2013)
Taoufik Chouta, Jean-Luc Danger, Laurent Sauvage, Tarik Graba
A Small and High-Performance Coprocessor for Fingerprint Match-on-Card. DSD (2012)
Shivam Bhasin, Sylvain Guilley, Youssef Souissi, Tarik Graba, Jean-Luc Danger
Efficient Dual-Rail Implementations in FPGA Using Block RAMs. ReConFig (2011)
Nidhal Selmane, Shivam Bhasin, Sylvain Guilley, Tarik Graba, Jean-Luc Danger
WDDL is Protected against Setup Time Violation Attacks. FDTC (2009)
Anthony Kolar, Olivier Romain, Jade Ayoub, David Faura, Sylvain Viateur, Bertrand Granado, Tarik Graba
A System for an Accurate 3D Reconstruction in Video Endoscopy Capsule. EURASIP J. Embed. Syst. 2009 (2009)
Shivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, Yves Mathieu, Maxime Nassar, Laurent Sauvage, Nidhal Selmane
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow. ReConFig (2009)
Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Tarik Graba, Yves Mathieu
Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs. SSIRI (2008)
Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Laurent Sauvage, Philippe Hoogvorst, Maxime Nassar, Tarik Graba, Vinh-Nga Vong
Place-and-Route Impact on the Security of DPL Designs in FPGAs. HOST (2008)
Anthony Kolar, Tarik Graba, Andréa Pinna, Olivier Romain, Bertrand Granado, Thomas Ea
An Integrated Digital Architecture for the Real-time Reconstruction in a VSiP Sensor. ICECS (2006)