Maxime Nassar

Publication Activity (10 Years)

Years Active: 2008-2012
Publications (10 Years): 0

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Publications

Youssef Souissi, Shivam Bhasin, Sylvain Guilley, Maxime Nassar, Jean-Luc Danger
Towards Different Flavors of Combined Side Channel Attacks. CT-RSA (2012)
Maxime Nassar, Youssef Souissi, Sylvain Guilley, Jean-Luc Danger
RSM: A small and fast countermeasure for AES, secure against 1st and 2nd-order zero-offset SCAs. DATE (2012)
Maxime Nassar, Sylvain Guilley, Jean-Luc Danger
Formal Analysis of the Entropy / Security Trade-off in First-Order Masking Countermeasures against Side-Channel Attacks. IACR Cryptol. ePrint Arch. 2011 (2011)
Nicolas Debande, Youssef Souissi, Maxime Nassar, Sylvain Guilley, Thanh-Ha Le, Jean-Luc Danger
"Re-synchronization by moments": An efficient solution to align Side-Channel traces. WIFS (2011)
Youssef Souissi, Jean-Luc Danger, Sylvain Guilley, Shivam Bhasin, Maxime Nassar
Embedded systems security: An evaluation methodology against Side Channel Attacks. DASIP (2011)
Maxime Nassar, Sylvain Guilley, Jean-Luc Danger
Formal Analysis of the Entropy / Security Trade-off in First-Order Masking Countermeasures against Side-Channel Attacks. INDOCRYPT (2011)
Maxime Nassar, Youssef Souissi, Sylvain Guilley, Jean-Luc Danger
"Rank Correction": A New Side-Channel Approach for Secret Key Recovery. InfoSecHiComNet (2011)
Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu
Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics. Int. J. Reconfigurable Comput. 2010 (2010)
Maxime Nassar, Shivam Bhasin, Jean-Luc Danger, Guillaume Duc, Sylvain Guilley
BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation. DATE (2010)
Youssef Souissi, Maxime Nassar, Sylvain Guilley, Jean-Luc Danger, Florent Flament
First Principal Components Analysis: A New Side Channel Distinguisher. ICISC (2010)
Laurent Sauvage, Sylvain Guilley, Jean-Luc Danger, Yves Mathieu, Maxime Nassar
Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints. DATE (2009)
Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu
DPL on Stratix II FPGA: What to Expect?. ReConFig (2009)
Shivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, Yves Mathieu, Maxime Nassar, Laurent Sauvage, Nidhal Selmane
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow. ReConFig (2009)
Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Laurent Sauvage, Philippe Hoogvorst, Maxime Nassar, Tarik Graba, Vinh-Nga Vong
Place-and-Route Impact on the Security of DPL Designs in FPGAs. HOST (2008)