Yves Mathieu

Publication Activity (10 Years)

Years Active: 1988-2023
Publications (10 Years): 9

Top Topics

Hardware Architecture

Design Methodology

Formal Evaluation

Top Venues

IEEE Trans. Computers

Publications

Guillaume Soudais, Tarik Graba, Yves Mathieu, Sébastien Bigo
Jitter Compensation Mechanism for Dynamic Deterministic Networks. OFC (2023)
Sofiane Takarabt, Sylvain Guilley, Youssef Souissi, Khaled Karray, Laurent Sauvage, Yves Mathieu
Formal Evaluation and Construction of Glitch-resistant Masked Functions. HOST (2021)
Ville Yli-Mäyry, Rei Ueno, Noriyuki Miura, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Naofumi Homma
Diffusional Side-Channel Leakage From Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE. IEEE Trans. Inf. Forensics Secur. 16 (2021)
Rei Ueno, Naofumi Homma, Sumio Morioka, Noriyuki Miura, Kohei Matsuda, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger
High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. IEEE Trans. Computers 69 (4) (2020)
Sofiane Takarabt, Alexander Schaub, Adrien Facon, Sylvain Guilley, Laurent Sauvage, Youssef Souissi, Yves Mathieu
Cache-Timing Attacks Still Threaten IoT Devices. C2SI (2019)
Jean-Luc Danger, Risa Yashiro, Tarik Graba, Yves Mathieu, Abdelmalek Si-Merabet, Kazuo Sakiyama, Noriyuki Miura, Makoto Nagata
Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology. DSD (2018)
Sofiane Takarabt, Kais Chibani, Adrien Facon, Sylvain Guilley, Yves Mathieu, Laurent Sauvage, Youssef Souissi
Pre-silicon Embedded System Evaluation as New EDA Tool for Security Verification. IVSW (2018)
Xuan Thuy Ngo, Jean-Luc Danger, Sylvain Guilley, Tarik Graba, Yves Mathieu, Zakaria Najm, Shivam Bhasin
Cryptographically Secure Shield for Security IPs Protection. IEEE Trans. Computers 66 (2) (2017)
Sumanta Chaudhuri, Tarik Graba, Yves Mathieu
Multi-Valued Routing Tracks for FPGAs in 28nm FDSOI Technology. CoRR (2016)
Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger
Countering early propagation and routing imbalance of DPL designs in a tree-based FPGA. ICICDT (2015)
Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Habib Mehrez
Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security. FPL (2014)
Jean-Michel Cioranesco, Jean-Luc Danger, Tarik Graba, Sylvain Guilley, Yves Mathieu, David Naccache, Xuan Thuy Ngo
Cryptographically secure shields. HOST (2014)
Shivam Bhasin, Jean-Luc Danger, Tarik Graba, Yves Mathieu, Daisuke Fujimoto, Makoto Nagata
Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology. ES4CPS@DATE (2014)
Molka Ben-Romdhane, Tarik Graba, Jean-Luc Danger, Yves Mathieu
Design methodology of an ASIC TRNG based on an open-loop delay chain. NEWCAS (2013)
Zouha Cherif, Jean-Luc Danger, Florent Lozach, Yves Mathieu, Lilian Bossuet
Evaluation of delay PUFs on CMOS 65 nm technology: ASIC vs FPGA. HASP@ISCA (2013)
Laurent Sauvage, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu
Blind Cartography for Side Channel Attacks: Cross-Correlation Cartography. Int. J. Reconfigurable Comput. 2012 (2012)
Mariem Slimani, Philippe Matherat, Yves Mathieu
A dual threshold voltage technique for glitch minimization. ICECS (2012)
Stéphane Mancini, Zahir Larabi, Yves Mathieu, Tomasz Toczek, Lionel Pierrefeu
Exploration of 3D grid caching strategies for ray-shooting. J. Real Time Image Process. 7 (1) (2012)
Laurent Sauvage, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu
Cross-Correlation Cartography. ReConFig (2010)
Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu
Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics. Int. J. Reconfigurable Comput. 2010 (2010)
Stéphane Mancini, Lionel Pierrefeu, Zahir Larabi, Yves Mathieu
Calibrating a predictive cache emulator for SoC design. AHS (2010)
Asmaa Al-Naqi, Ahmet T. Erdogan, Tughrul Arslan, Yves Mathieu
Balancing exploration and exploitation in an adaptive three-dimensional cellular genetic algorithm via a probabilistic selection operator. AHS (2010)
Laurent Sauvage, Sylvain Guilley, Yves Mathieu
Electromagnetic Radiations of FPGAs: High Spatial Resolution Cartography and Attack on a Cryptographic Module. ACM Trans. Reconfigurable Technol. Syst. 2 (1) (2009)
Laurent Sauvage, Sylvain Guilley, Jean-Luc Danger, Yves Mathieu, Maxime Nassar
Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints. DATE (2009)
Zahir Larabi, Yves Mathieu, Stéphane Mancini
High Efficiency Reconfigurable Cache for Image Processing. ERSA (2009)
Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu
DPL on Stratix II FPGA: What to Expect?. ReConFig (2009)
Shivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, Yves Mathieu, Maxime Nassar, Laurent Sauvage, Nidhal Selmane
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow. ReConFig (2009)
Zahir Larabi, Yves Mathieu, Stéphane Mancini
Efficient Data Access Management for FPGA-Based Image Processing SoCs. IEEE International Workshop on Rapid System Prototyping (2009)
Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Tarik Graba, Yves Mathieu
Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs. SSIRI (2008)
Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Renaud Pacalet, Yves Mathieu
Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors. IEEE Des. Test Comput. 24 (6) (2007)
Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet
The "Backend Duplication" Method. CHES (2005)
Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet, Jean Provost
CMOS Structures Suitable for Secured Hardware. DATE (2004)
Christophe Cunat, Jean Gobert, Yves Mathieu
A coprocessor for real-time MPEG4 facial animation on mobiles. ESTIMedia (2003)
Paul Winser, Thierry Bonnet, Dominique Dumont, Yves Mathieu
Architectures for Mass Market 3D Displays. Eurographics (1988)