Evaluation of delay PUFs on CMOS 65 nm technology: ASIC vs FPGA.
Zouha CherifJean-Luc DangerFlorent LozachYves MathieuLilian BossuetPublished in: HASP@ISCA (2013)
Keyphrases
- nm technology
- single chip
- power dissipation
- low power
- high speed
- power consumption
- hardware implementation
- hardware architecture
- low cost
- circuit design
- digital signal processing
- image analysis
- low power consumption
- relational databases
- pattern matching
- signal processing
- neural network
- integrated circuit
- design methodology
- general purpose
- cmos technology