Noriyuki Miura

ORCID

Publication Activity (10 Years)

Years Active: 2004-2024
Publications (10 Years): 47

Top Venues

IEEE J. Solid State Circuits

ISSCC

IEICE Trans. Electron.

ASP-DAC

Publications

Kazuki Minamiguchi, Yoshihiro Midoh, Noriyuki Miura, Jun Shiomi
Modeling of Tamper Resistance to Electromagnetic Side-channel Attacks on Voltage-scaled Circuits. ASPDAC (2024)
Itsuki Takada, Daiki Nitto, Yoshihiro Midoh, Noriyuki Miura, Jun Shiomi, Ryoichi Shinkuma
Edge-Oriented Point Cloud Compression by Moving Object Detection for Realtime Smart Monitoring. CCNC (2024)
Dehua Liang, Jun Shiomi, Noriyuki Miura, Hiromitsu Awano
StrideHD: A Binary Hyperdimensional Computing System Utilizing Window Striding for Image Classification. IEEE Open J. Circuits Syst. 5 (2024)
Haruka Hirata, Daiki Miyahara, Victor Arribas, Yang Li, Noriyuki Miura, Svetla Nikova, Kazuo Sakiyama
All You Need Is Fault: Zero-Value Attacks on AES and a New λ-Detection M&M. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2024 (1) (2024)
Kotaro Naruse, Takayuki Ueda, Jun Shiomi, Yoshihiro Midoh, Noriyuki Miura
A Self-Programming PUF Harvesting the High-Energy Plasma During Fabrication. ISSCC (2023)
Noriyuki Miura, Kotaro Naruse, Jun Shiomi, Yoshihiro Midoh, Tetsuya Hirose, Takaaki Okidono, Takuji Miki, Makoto Nagata
A Triturated Sensing System. ISSCC (2023)
Dehua Liang, Hiromitsu Awano, Noriyuki Miura, Jun Shiomi
DependableHD: A Hyperdimensional Learning Framework for Edge-Oriented Voltage-Scaled Circuits. ASP-DAC (2023)
Haruka Hirata, Daiki Miyahara, Victor Arribas, Yang Li, Noriyuki Miura, Svetla Nikova, Kazuo Sakiyama
All You Need Is Fault: Zero-Value Attacks on AES and a New λ-Detection M&M. IACR Cryptol. ePrint Arch. 2023 (2023)
Dehua Liang, Jun Shiomi, Noriyuki Miura, Hiromitsu Awano
DistriHD: A Memory Efficient Distributed Binary Hyperdimensional Computing Architecture for Image Classification. ASP-DAC (2022)
Takuma Okada, Yoshihiro Midoh, Koji Nakamae, Noriyuki Miura
Accurate measurement of charge density in nanoscale particles using an aperture optimization of Fourier based phase reconstruction. Computational Imaging (2022)
Dehua Liang, Jun Shiomi, Noriyuki Miura, Masanori Hashimoto, Hiromitsu Awano
A Hardware Efficient Reservoir Computing System Using Cellular Automata and Ensemble Bloom Filter. IEICE Trans. Inf. Syst. (7) (2022)
Makoto Nagata, Takuji Miki, Noriyuki Miura
Physical Attack Protection Techniques for IC Chip Level Hardware Security. IEEE Trans. Very Large Scale Integr. Syst. 30 (1) (2022)
Annjhih Hsiao, Takao Takenouchi, Hiroaki Kikuchi, Kazuo Sakiyama, Noriyuki Miura
More Accurate and Robust PRNU-Based Source Camera Identification with 3-Step 3-Class Approach. IWDW (2021)
Ville Yli-Mäyry, Rei Ueno, Noriyuki Miura, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Naofumi Homma
Diffusional Side-Channel Leakage From Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE. IEEE Trans. Inf. Forensics Secur. 16 (2021)
Shoei Nashimoto, Daisuke Suzuki, Noriyuki Miura, Tatsuya Machida, Kohei Matsuda, Makoto Nagata
Low-cost distance-spoofing attack on FMCW radar and its feasibility study on countermeasure. J. Cryptogr. Eng. 11 (3) (2021)
Tomoki Uemura, Yohei Watanabe, Yang Li, Noriyuki Miura, Mitsugu Iwamoto, Kazuo Sakiyama, Kazuo Ohta
A Key Recovery Algorithm Using Random Key Leakage from AES Key Schedule. ISITA (2020)
Takuji Miki, Noriyuki Miura, Hiroki Sonoda, Kento Mizuta, Makoto Nagata
A Random Interrupt Dithering SAR Technique for Secure ADC Against Reference-Charge Side-Channel Attack. IEEE Trans. Circuits Syst. II Express Briefs (1) (2020)
Rei Ueno, Naofumi Homma, Sumio Morioka, Noriyuki Miura, Kohei Matsuda, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger
High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. IEEE Trans. Computers 69 (4) (2020)
Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. IEEE J. Solid State Circuits 55 (10) (2020)
Yoshihide Komatsu, Akinori Shinmyo, Mayuko Fujita, Tsuyoshi Hiraki, Kouichi Fukuda, Noriyuki Miura, Makoto Nagata
A 0.6-V Adaptive Voltage Swing Serial Link Transmitter Using Near Threshold Body Bias Control and Jitter Estimation. IEICE Trans. Electron. (10) (2020)
Kazuo Sakiyama, Tatsuya Fujii, Kohei Matsuda, Noriyuki Miura
Flush Code Eraser: Fast Attack Response Invalidating Cryptographic Sensitive Data. IEEE Embed. Syst. Lett. 12 (2) (2020)
Takuji Miki, Noriyuki Miura, Hiroki Sonoda, Kento Mizuta, Makoto Nagata
A Random Interrupt Dithering SAR Technique for Secure ADC against Reference-Charge Side-Channel Attack. ISCAS (2020)
Yang Li, Ryota Hatano, Sho Tada, Kohei Matsuda, Noriyuki Miura, Takeshi Sugawara, Kazuo Sakiyama
Side-Channel Leakage of Alarm Signal for a Bulk-Current-Based Laser Sensor. Inscrypt (2019)
Noriyuki Miura, Tatsuya Machida, Kohei Matsuda, Makoto Nagata, Shoei Nashimoto, Daisuke Suzuki
A Low-Cost Replica-Based Distance-Spoofing Attack on mmWave FMCW Radar. ASHES@CCS (2019)
Takuji Miki, Noriyuki Miura, Makoto Nagata
Physical Random Number Generator Utilizing SAR Technique for Secure Implementation on Sensor Nodes. IEICE Trans. Electron. (7) (2019)
Takuji Miki, Makoto Nagata, Akihiro Tsukioka, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs. 3DIC (2019)
Makoto Nagata, Takuji Miki, Noriyuki Miura
On-Chip Physical Attack Protection Circuits for Hardware Security : Invited Paper. CICC (2019)
Takeshi Sugawara, Natsu Shoji, Kazuo Sakiyama, Kohei Matsuda, Noriyuki Miura, Makoto Nagata
Side-channel leakage from sensor-based countermeasures against fault injection attack. Microelectron. J. 90 (2019)
Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
A Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. A-SSCC (2019)
Daisuke Fujimoto, Shota Nin, Yu-ichi Hayashi, Noriyuki Miura, Makoto Nagata, Tsutomu Matsumoto
A Demonstration of a HT-Detection Method Based on Impedance Measurements of the Wiring Around ICs. IEEE Trans. Circuits Syst. II Express Briefs (10) (2018)
Kohei Matsuda, Tatsuya Fujii, Natsu Shoji, Takeshi Sugawara, Kazuo Sakiyama, Yu-ichi Hayashi, Makoto Nagata, Noriyuki Miura
/Cell Distributed Bulk-Current Sensor and Secure Flush Code Eraser Against Laser Fault Injection Attack on Cryptographic Processor. IEEE J. Solid State Circuits 53 (11) (2018)
Jean-Luc Danger, Risa Yashiro, Tarik Graba, Yves Mathieu, Abdelmalek Si-Merabet, Kazuo Sakiyama, Noriyuki Miura, Makoto Nagata
Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology. DSD (2018)
Noriyuki Miura, Masanori Takahashi, Kazuki Nagatomo, Makoto Nagata
Chip-Package-Board Interactive PUF Utilizing Coupled Chaos Oscillators With Inductor. IEEE J. Solid State Circuits 53 (10) (2018)
Kohei Matsuda, Tatsuya Fujii, Natsu Shoji, Takeshi Sugawara, Kazuo Sakiyama, Yu-ichi Hayashi, Makoto Nagata, Noriyuki Miura
/cell distributed bulk-current sensor and secure flush code eraser against laser fault injection attack. ISSCC (2018)
Noriyuki Miura, Masanori Takahashi, Kazuki Nagatomo, Makoto Nagata
Chaos, deterministic non-periodic flow, for chip-package-board interactive PUF. A-SSCC (2017)
Takuji Miki, Noriyuki Miura, Kento Mizuta, Shiro Dosho, Makoto Nagata
A 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter Utilizing Two-Step Transition Inverter Delay Lines in 28 nm CMOS. IEICE Trans. Electron. (6) (2017)
Wei He, Jakub Breier, Shivam Bhasin, Noriyuki Miura, Makoto Nagata
An FPGA-compatible PLL-based sensor against fault injection attack. ASP-DAC (2017)
Naofumi Homma, Yu-ichi Hayashi, Noriyuki Miura, Daisuke Fujimoto, Makoto Nagata, Takafumi Aoki
Design Methodology and Validity Verification for a Reactive Countermeasure Against EM Attacks. J. Cryptol. 30 (2) (2017)
Makoto Nagata, Daisuke Fujimoto, Noriyuki Miura, Naofumi Homma, Yu-ichi Hayashi, Kazuo Sakiyama
Protecting cryptographic integrated circuits with side-channel information. IEICE Electron. Express 14 (2) (2017)
Takeshi Sugawara, Natsu Shoji, Kazuo Sakiyama, Kohei Matsuda, Noriyuki Miura, Makoto Nagata
Exploiting Bitflip Detector for Non-invasive Probing and its Application to Ineffective Fault Analysis. FDTC (2017)
Noriyuki Miura, Shijia Liu, Tsuyoshi Watanabe, Shigeki Imai, Makoto Nagata
x-point multi-layer metal nano-dot structure. ISSCC (2017)
Makoto Ikeda, Noriyuki Miura
Introduction to the Special Section on the 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits 51 (10) (2016)
Noriyuki Miura, Zakaria Najm, Wei He, Shivam Bhasin, Xuan Thuy Ngo, Makoto Nagata, Jean-Luc Danger
PLL to the rescue: a novel EM fault countermeasure. DAC (2016)
Kohei Matsuda, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Tatsuya Fujii, Kazuo Sakiyama
On-chip substrate-bounce monitoring for laser-fault countermeasure. AsianHOST (2016)
Takuji Miki, Noriyuki Miura, Kento Mizuta, Shiro Dosho, Makoto Nagata
A 500MHz-BW -52.5dB-THD Voltage-to-Time Converter utilizing a two-step transition inverter. ESSCIRC (2016)
Wei He, Jakub Breier, Shivam Bhasin, Noriyuki Miura, Makoto Nagata
Ring Oscillator under Laser: Potential of PLL-based Countermeasure against Laser Fault Injection. FDTC (2016)
Noriyuki Miura, Shivam Bhasin
Attack sensing against EM leakage and injection. ISOCC (2016)
Daisuke Fujimoto, Noriyuki Miura, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Makoto Nagata
A DPA/DEMA/LEMA-resistant AES cryptographic processor with supply-current equalizer and micro EM probe sensor. ASP-DAC (2015)
Noriyuki Miura, Shiro Dosho, Hiroyuki Tezuka, Takuji Miki, Daisuke Fujimoto, Takuya Kiriyama, Makoto Nagata
A 1 mm Pitch 80 × 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan. IEEE J. Solid State Circuits 50 (11) (2015)
Noriyuki Miura, Daisuke Fujimoto, Makoto Nagata, Naofumi Homma, Yu-ichi Hayashi, Takafumi Aoki
EM attack sensor: concept, circuit, and design-automation methodology. DAC (2015)
Kohki Taniguchi, Noriyuki Miura, Taisuke Hayashi, Makoto Nagata
At-Product-Test Dedicated Adaptive supply-resonance suppression. VTS (2015)
Taisuke Hayashi, Noriyuki Miura, Kumpei Yoshikawa, Makoto Nagata
A passive supply-resonance suppression filter utilizing inductance-enhanced coupled bonding-wire coils. VLSI-DAT (2014)
Naofumi Homma, Yu-ichi Hayashi, Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Makoto Nagata, Takafumi Aoki
EM Attack Is Non-invasive? - Design Methodology and Validity Verification of EM Attack Sensor. CHES (2014)
Daisuke Fujimoto, Daichi Tanaka, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Naofumi Homma, Shivam Bhasin, Jean-Luc Danger
Side-channel leakage on silicon substrate of CMOS cryptographic chip. HOST (2014)
Naoya Azuma, Shunsuke Shimazaki, Noriyuki Miura, Makoto Nagata, Tomomitsu Kitamura, Satoru Takahashi, Motoki Murakami, Kazuaki Hori, Atsushi Nakamura, Kenta Tsukamoto, Mizuki Iwanami, Eiji Hankui, Sho Muroga, Yasushi Endo, Satoshi Tanaka, Masahiro Yamaguchi
Chip Level Simulation of Substrate Noise Coupling and Interference in RF ICs with CMOS Digital Noise Emulator. IEICE Trans. Electron. (6) (2014)
Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama, Thanh-Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Shivam Bhasin, Jean-Luc Danger
Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage. IEICE Trans. Electron. (4) (2014)
Makoto Nagata, Daisuke Fujimoto, Noriyuki Miura
On-Chip Monitoring for In-Place Diagnosis of Undesired Power Domain Problems in IC Chips. ATS (2014)
Naofumi Homma, Yu-ichi Hayashi, Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Makoto Nagata, Takafumi Aoki
EM Attack Is Non-Invasive? - Design Methodology and Validity Verification of EM Attack Sensor. IACR Cryptol. ePrint Arch. 2014 (2014)
Atsutake Kosuge, Wataru Mizuhara, Tsunaaki Shidei, Tsutomu Takeya, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda
A 0.15-mm-Thick Noncontact Connector for MIPI Using a Vertical Directional Coupler. IEEE J. Solid State Circuits 49 (1) (2014)
Noriyuki Miura, Daisuke Fujimoto, Rie Korenaga, Kohei Matsuda, Makoto Nagata
An intermittent-driven supply-current equalizer for 11x and 4x power-overhead savings in CPA-resistant 128bit AES cryptographic processor. A-SSCC (2014)
Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Makoto Nagata
A local EM-analysis attack resistant cryptographic engine with fully-digital oscillator-based tamper-access sensor. VLSIC (2014)
Noriyuki Miura, Shiro Dosho, Satoshi Takaya, Daisuke Fujimoto, Takuya Kiriyama, Hiroyuki Tezuka, Takuji Miki, Hiroto Yanagawa, Makoto Nagata
12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan. ISSCC (2014)
Noriyuki Miura, Yusuke Koizumi, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface. IEEE Micro 33 (6) (2013)
Noriyuki Miura, Mitsuko Saito, Masao Taguchi, Tadahiro Kuroda
A 6nW inductive-coupling wake-up transceiver for reducing standby power of non-contact memory card by 500×. ISSCC (2013)
Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. COOL Chips (2013)
Naoya Azuma, Shunsuke Shimazaki, Noriyuki Miura, Makoto Nagata, Tomomitsu Kitamura, Satoru Takahashi, Motoki Murakami, Kazuaki Hori, Atsushi Nakamura, Kenta Tsukamoto, Mizuki Iwanami, Eiji Hankui, Sho Muroga, Yasushi Endo, Satoshi Tanaka, Masahiro Yamaguchi
Measurements and simulation of substrate noise coupling in RF ICs with CMOS digital noise emulator. EMC Compo (2013)
Atsutake Kosuge, Wataru Mizuhara, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda
A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched Transmission Line Couplers and Dicode partial-response channel transceivers. ASP-DAC (2013)
Yasuhiro Take, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
3D clock distribution using vertically/horizontally-coupled resonators. ISSCC (2013)
Yusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links. FPL (2013)
Tsutomu Takeya, Lan Nan, Shinya Nakano, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
A 12-Gb/s Non-Contact Interface With Coupled Transmission Lines. IEEE J. Solid State Circuits 48 (3) (2013)
Wataru Mizuhara, Tsunaaki Shidei, Atsutake Kosuge, Tsutomu Takeya, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda
A 0.15mm-thick non-contact connector for MIPI using vertical directional coupler. ISSCC (2013)
Kumpei Yoshikawa, Yuji Harada, Noriyuki Miura, Noriaki Takeda, Yoshiyuki Saito, Makoto Nagata
Immunity evaluation of inverter chains against RF power on power delivery network. EMC Compo (2013)
Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. Hot Chips Symposium (2013)
Yasuhisa Shimazaki, Noriyuki Miura, Tadahiro Kuroda
A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors. COOL Chips (2012)
Kiichi Niitsu, Shusuke Kawai, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
A 65fJ/b Inter-Chip Inductive-Coupling Data Transceivers Using Charge-Recycling Technique for Low-Power Inter-Chip Communication in 3-D System Integration. IEEE Trans. Very Large Scale Integr. Syst. 20 (7) (2012)
Andrzej Radecki, Hayun Chung, Yoichi Yoshida, Noriyuki Miura, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda
Wireless Power Transmission for Non-contact Wafer-Level Testing. IEICE Trans. Electron. (4) (2012)
Andrzej Radecki, Yuxiang Yuan, Noriyuki Miura, Iori Aikawa, Yasuhiro Take, Hiroki Ishikuro, Tadahiro Kuroda
Simultaneous 6-Gb/s Data and 10-mW Power Transmission Using Nested Clover Coils for Noncontact Memory Card. IEEE J. Solid State Circuits 47 (10) (2012)
Atsutake Kosuge, Wataru Mizuhara, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda
A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched transmission line couplers and Dicode partial-response channel transceivers. CICC (2012)
Noriyuki Miura, Mitsuko Saito, Tadahiro Kuroda
/(TB/s) QDR Inductive-Coupling Interface Between 65-nm CMOS Logic and Emulated 100-nm DRAM. IEEE J. Emerg. Sel. Topics Circuits Syst. 2 (2) (2012)
Yusuke Koizumi, Hideharu Amano, Hiroki Matsutani, Noriyuki Miura, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect. FPT (2012)
Andrzej Radecki, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
Rotary Coding for Power Reduction and S/N Improvement in Inductive-Coupling Data Communication. IEEE J. Solid State Circuits 47 (11) (2012)
Hayun Chung, Andrzej Radecki, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
A 0.025-0.45 W 60%-Efficiency Inductive-Coupling Power Transceiver With 5-Bit Dual-Frequency Feedforward Control for Non-Contact Memory Cards. IEEE J. Solid State Circuits 47 (10) (2012)
Won-Joo Yun, Shinya Nakano, Wataru Mizuhara, Atsutake Kosuge, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line. ISSCC (2012)
Yasuhiro Take, Hayun Chung, Noriyuki Miura, Tadahiro Kuroda
Simultaneous data and power transmission using nested clover coils. ASP-DAC (2012)
Yasuhiro Take, Noriyuki Miura, Tadahiro Kuroda
Inductively-Coupled Injection-Locking CDR for High-Speed DRAM Interface. IEEE J. Solid State Circuits 46 (11) (2011)
Andrzej Radecki, Hayun Chung, Yoichi Yoshida, Noriyuki Miura, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda
inductive power transfer for non-contact wafer-level testing. ISSCC (2011)
Noriyuki Miura, Tsunaaki Shidei, Yuxiang Yuan, Shusuke Kawai, Keita Takatsu, Yuji Kiyota, Yuichi Asano, Tadahiro Kuroda
A 0.55 V 10 fJ/bit Inductive-Coupling Data Link and 0.7 V 135 fJ/Cycle Clock Link With Dual-Coil Transmission Scheme. IEEE J. Solid State Circuits 46 (4) (2011)
Noriyuki Miura, Yasuhiro Take, Mitsuko Saito, Yoichi Yoshida, Tadahiro Kuroda
0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND Flash memory stacking. ISSCC (2011)
Tsutomu Takeya, Lan Nan, Shinya Nakano, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
A 12Gb/s non-contact interface with coupled transmission lines. ISSCC (2011)
Andrzej Radecki, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
Rotary coding for power reduction and S/N improvement in inductive-coupling data communication. A-SSCC (2011)
Noriyuki Miura, Kazutaka Kasuga, Mitsuko Saito, Tadahiro Kuroda
/Tb/s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM. ISSCC (2010)
Mitsuko Saito, Noriyuki Miura, Tadahiro Kuroda
A 2Gb/s 1.8pJ/b/chip inductive-coupling through-chip bus for 128-Die NAND-Flash memory stacking. ISSCC (2010)
Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda
2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking. IEEE J. Solid State Circuits 45 (1) (2010)
Mitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
47% Power Reduction and 91% Area Reduction in Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2010)
Noriyuki Miura, Yoshinori Kohama, Yasufumi Sugimori, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda
A High-Speed Inductive-Coupling Link With Burst Transmission. IEEE J. Solid State Circuits 44 (3) (2009)
Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, Hideharu Amano
MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link. FPL (2009)
Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking. CICC (2009)
Yasufumi Sugimori, Yoshinori Kohama, Mitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda
A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking. ISSCC (2009)
Noriyuki Miura, Hiroki Ishikuro, Kiichi Niitsu, Takayasu Sakurai, Tadahiro Kuroda
A 0.14 pJ/b Inductive-Coupling Transceiver With Digitally-Controlled Precise Pulse Shaping. IEEE J. Solid State Circuits 43 (1) (2008)
Daisuke Mizoguchi, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
Constant Magnetic Field Scaling in Inductive-Coupling Data Link. IEICE Trans. Electron. (2) (2008)

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Noriyuki Miura