Toshihiro Katashita

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 7

Top Topics

Authentication Scheme

Vector Quantization

Fpga Implementation

Top Venues

IEICE Trans. Inf. Syst.

ACNS Workshops (1)

IEICE Trans. Commun.

Publications

Tatsuya Oyama, Mika Sakai, Yohei Hori, Toshihiro Katashita, Takeshi Fujino
FPGA Implementation of Physically Unclonable Functions Based on Multi-threshold Delay Time Measurement Method to Mitigate Modeling Attacks. ACNS Workshops (1) (2024)
Hiroshi Fuketa, Toshihiro Katashita, Yohei Hori, Masakazu Hioki
Multiplication-Free Lookup-Based CNN Accelerator Using Residual Vector Quantization and Its FPGA Implementation. IEEE Access 12 (2024)
Yusuke Yano, Kengo Iokibe, Toshiaki Teshima, Yoshitaka Toyota, Toshihiro Katashita, Yohei Hori
Evaluation of Side-Channel Leakage Simulation by Using EMC Macro-Model of Cryptographic Devices. IEICE Trans. Commun. (2) (2021)
Yasuhiro Ogasahara, Yohei Hori, Toshihiro Katashita, Tomoki Iizuka, Hiromitsu Awano, Makoto Ikeda, Hanpei Koike
Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge-Response pair acquisition using Built-In Self-Test before shipping. Integr. 71 (2020)
Risa Yashiro, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama
A Deep Learning Attack Countermeasure with Intentional Noise for a PUF-Based Authentication Scheme. SECITC (2019)
Toshihiro Katashita, Masakazu Hioki, Yohei Hori, Hanpei Koike
Development of an Evaluation Platform and Performance Experimentation of Flex Power FPGA Device. IEICE Trans. Inf. Syst. (2) (2018)
Toshihiro Katashita, Yohei Hori, Yasuhiro Ogasahara
Prototype of USB stick-sized PUF module for authentication and key generation. GCCE (2017)
Sho Endo, Yang Li, Naofumi Homma, Kazuo Sakiyama, Kazuo Ohta, Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Jean-Luc Danger, Takafumi Aoki
A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation. IEEE Trans. Very Large Scale Integr. Syst. 23 (8) (2015)
Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama, Thanh-Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Shivam Bhasin, Jean-Luc Danger
Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage. IEICE Trans. Electron. (4) (2014)
Yohei Hori, Hyunho Kang, Toshihiro Katashita, Akashi Satoh, Shin-ichi Kawamura, Kazukuni Kobara
Evaluation of Physical Unclonable Functions for 28-nm Process Field-Programmable Gate Arrays. J. Inf. Process. 22 (2) (2014)
Yohei Hori, Toshihiro Katashita, Kazukuni Kobara
Energy and area saving effect of Dynamic Partial Reconfiguration on a 28-nm process FPGA. GCCE (2013)
Yohei Hori, Toshihiro Katashita, Hirofumi Sakane, Kenji Toda, Akashi Satoh
Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption. IEICE Trans. Inf. Syst. (11) (2013)
Toshihiro Katashita, Akihiko Sasaki, Yohei Hori
A novel smart card development platform for evaluating physical attacks and PUFs. GCCE (2013)
Daisuke Fujimoto, Toshihiro Katashita, Akihiko Sasaki, Yohei Hori, Akashi Satoh, Makoto Nagata
A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Miroslav Knezevic, Kazuyuki Kobayashi, Jun Ikegami, Shin'ichiro Matsuo, Akashi Satoh, Ünal Koçabas, Junfeng Fan, Toshihiro Katashita, Takeshi Sugawara, Kazuo Sakiyama, Ingrid Verbauwhede, Kazuo Ohta, Naofumi Homma, Takafumi Aoki
Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates. IEEE Trans. Very Large Scale Integr. Syst. 20 (5) (2012)
Takeshi Sugawara, Daisuke Suzuki, Toshihiro Katashita
Circuit Simulation for Fault Sensitivity Analysis and Its Application to Cryptographic LSI. FDTC (2012)
Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Akihiro T. Sasaki, Yohei Hori, Akashi Satoh
A fast power current analysis methodology using capacitor charging model for side channel attack evaluation. HOST (2011)
Yohei Hori, Hyunho Kang, Toshihiro Katashita, Akashi Satoh
Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable Function. ReConFig (2011)
Yohei Hori, Takahiro Yoshida, Toshihiro Katashita, Akashi Satoh
Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs. ReConFig (2010)
Akashi Satoh, Toshihiro Katashita, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki
Hardware Implementations of Hash Function Luffa. HOST (2010)
Toshihiro Katashita, Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki
Development of side-channel attack standard evaluation environment. ECCTD (2009)
Toshihiro Katashita, Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki
Enhanced Correlation Power Analysis Using Key Screening Technique. ReConFig (2008)
Toshihiro Katashita, Yoshinori Yamaguchi, Atusi Maeda, Kenji Toda
FPGA-Based Intrusion Detection System for 10 Gigabit Ethernet. IEICE Trans. Inf. Syst. (12) (2007)
Toshihiro Katashita, Atusi Maeda, Kenji Toda, Yoshinori Yamaguchi
A Method of Generating Highly Efficient String Matching Circuit for Intrusion Detection. FPL (2006)
Toshihiro Katashita, Atusi Maeda, Kenji Toda, Yoshinori Yamaguchi
Highly Efficient String Matching Circuit for IDS with FPGA. FCCM (2006)