Hanpei Koike

Publication Activity (10 Years)

Years Active: 1986-2023
Publications (10 Years): 8

Top Topics

Random Number Generator

Phase Contrast Microscopy

Top Venues

IEICE Trans. Inf. Syst.

IEEE Trans. Circuits Syst. I Regul. Pap.

VLSI Technology and Circuits

IEICE Electron. Express

Publications

Hiroshi Fuketa, Ippei Akita, Tomohiro Ishikawa, Hanpei Koike, Takahiro Mori
A Cryogenic CMOS Current Integrator and Correlation Double Sampling Circuit for Spin Qubit Readout. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (12) (2023)
Hiroshi Fuketa, Ippei Akita, Tomohiro Ishikawa, Hanpei Koike, Takahiro Mori
A Cryogenic CMOS Current Comparator for Spin Qubit Readout Achieving Fast Readout Time and High Current Resolution. VLSI Technology and Circuits (2022)
Yasuhiro Ogasahara, Yohei Hori, Toshihiro Katashita, Tomoki Iizuka, Hiromitsu Awano, Makoto Ikeda, Hanpei Koike
Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge-Response pair acquisition using Built-In Self-Test before shipping. Integr. 71 (2020)
Toshihiro Katashita, Masakazu Hioki, Yohei Hori, Hanpei Koike
Development of an Evaluation Platform and Performance Experimentation of Flex Power FPGA Device. IEICE Trans. Inf. Syst. (2) (2018)
Masakazu Hioki, Hanpei Koike
Low Overhead Design of Power Reconfigurable FPGA with Fine-Grained Body Biasing on 65-nm SOTB CMOS Technology. IEICE Trans. Inf. Syst. (12) (2016)
Yasuhiro Ogasahara, Yohei Hori, Hanpei Koike
Implementation of pseudo linear feedback shift register physical unclonable function on silicon. ISCAS (2016)
Yasuhiro Ogasahara, Tadashi Nakagawa, Toshihiro Sekigawa, Toshiyuki Tsutsumi, Hanpei Koike
control, low process variability, and steep SS with low on-current of new structure transistors to ultra-low voltage designs. IEICE Electron. Express 12 (15) (2015)
Yasuhiro Ogasahara, Yohei Hori, Hanpei Koike
Standard cell implementation of buskeeper PUF with symmetric inverters and neighboring cells for passing randomness tests. GCCE (2015)
Masakazu Hioki, Toshihiro Sekigawa, Tadashi Nakagawa, Hanpei Koike, Yohei Matsumoto, Takashi Kawanami, Toshiyuki Tsutsumi
Fully-functional FPGA prototype with fine-grain programmable body biasing. FPGA (2013)
Hideo Sakai, Shin-ichi O'Uchi, Takashi Matsukawa, Kazuhiko Endo, Yongxun Liu, Junichi Tsukada, Yuki Ishikawa, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara, Hiroki Ishikuro
High-Frequency Precise Characterization of Intrinsic FinFET Channel. IEICE Trans. Electron. (4) (2012)
Shin-ichi O'Uchi, Kazuhiko Endo, Takashi Matsukawa, Yongxun Liu, Tadashi Nakagawa, Yuki Ishikawa, Junichi Tsukada, Hiromi Yamauchi, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara
A 0.7-V Opamp in Scaled Low-Standby-Power FinFET Technology. IEICE Trans. Electron. (4) (2012)
Naoto Miyamoto, Yohei Matsumoto, Hanpei Koike, Tadayuki Matsumura, Kenichi Osada, Yaoko Nakagawa, Tadahiro Ohmi
Development of a CAD tool for 3D-FPGAs. 3DIC (2010)
Shin-ichi O'Uchi, Kazuhiko Endo, Yongxun Liu, Tadashi Nakagawa, Takashi Matsukawa, Yuki Ishikawa, Junichi Tsukada, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara
Realization of 0.7-V analog circuits by adaptive-Vt operation of FinFET. CICC (2010)
Shin-ichi O'Uchi, Kazuhiko Endo, Yongxun Liu, Tadashi Nakagawa, Takashi Matsukawa, Yuki Ishikawa, Junichi Tsukada, Hiromi Yamauchi, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara
0.5V FinFET SRAM with dynamic threshold control of pass gates for salvaging malfunctioned bits. ESSCIRC (2010)
Seid Hadi Rasouli, Hanpei Koike, Kaustav Banerjee
High-speed low-power FinFET based domino logic. ASP-DAC (2009)
Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Hanpei Koike, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa
Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations. ACM Trans. Reconfigurable Technol. Syst. 1 (1) (2008)
Shin-ichi O'Uchi, Meishoku Masahara, Kazuhiko Endo, Yongxun Liu, Takashi Matsukawa, Kunihiro Sakamoto, Toshihiro Sekigawa, Hanpei Koike, Eiichi Suzuki
FinFET-Based Flex-Vth SRAM Design for Drastic Standby-Leakage-Current Reduction. IEICE Trans. Electron. (4) (2008)
Takashi Kawanami, Masakazu Hioki, Yohei Matsumoto, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike
Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGA. IEICE Trans. Inf. Syst. (12) (2007)
Shin-ichi O'Uchi, Meishoku Masahara, Kunihiro Sakamoto, Kazuhiko Endo, Yongxun Liu, Takashi Matsukawa, Toshihiro Sekigawa, Hanpei Koike, Eiichi Suzuki
Flex-Pass-Gate SRAM Design for Static Noise Margin Enhancement Using FinFET-Based Technology. CICC (2007)
Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike
Performance and yield enhancement of FPGAs with within-die variation using multiple configurations. FPGA (2007)
Masakazu Hioki, Takashi Kawanami, Yohei Matsumoto, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike, Toshiyuki Tsutsumi
A Power Configurable Block Array Connected in Series as First Prototype Flex Power FPGA Chip. FPT (2007)
Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike
Evaluation of granularity on threshold voltage control in flex power FPGA. FPGA (2006)
Takashi Kawanami, Masakazu Hioki, Yohei Matsumoto, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike
components. FPT (2006)
Yohei Matsumoto, Hanpei Koike, Akira Masaki
FPGAs with multidimensional mesh topology. FPGA (2006)
Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike
Evaluation of granularity on threshold voltage control in flex power FPGA. FPT (2006)
Hanpei Koike, Toshihiro Sekigawa
XDXMOS: a novel technique for the double-gate MOSFETs logic circuits - to achieve high drive current and small input capacitance together. CICC (2005)
Takashi Kawanami, Masakazu Hioki, Hiroshi Nagase, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike
Preliminary Evaluation of Flex Power FPGA: A Power Reconfigurable Architecture with Fine Granularity. IEICE Trans. Inf. Syst. (8) (2004)
Takashi Kawanami, Masakazu Hioki, Hiroshi Nagase, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike
Preliminary performance analysis of flex power FPGA, a power reconfigurable device with fine granularity. FPGA (2004)
Hayato Yamana, Hanpei Koike, Yuetsu Kodama, Hirofumi Sakane, Yoshinori Yamaguchi
Fast Speculative Search Engine on the Highly Parallel Computer EM-X. SIGIR (1998)
Yuetsu Kodama, Hirofumi Sakane, Hanpei Koike, Mitsuhisa Sato, Shuichi Sakai, Yoshinori Yamaguchi
Parallel Execution of Radix Sort Program Using Fine-Grain Communication. IEEE PACT (1997)
Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka
Architecture of parallel management kernel for PIE64. Future Gener. Comput. Syst. 10 (1) (1994)
Jun'ichi Tatemura, Hanpei Koike, Hidehiko Tanaka
A Performance Debugger for a Parallel Logic Programming Language Fleng. Theory and Practice of Parallel Programming (1994)
Hidemoto Nakada, Takuya Araki, Hanpei Koike, Hidehiko Tanaka
A Fleng Compiler for PIE64. IFIP PACT (1994)
Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka
Multiple Threads in Cyclic Register Windows. ISCA (1993)
Kentaro Shimada, Hanpei Koike, Hidehiko Tanaka
UNIRED II: The High Performance Inference Processor for the Parallel Inference Machine PIE64. New Gener. Comput. 11 (3) (1993)
Jun'ichi Tatemura, Hanpei Koike, Hidehiko Tanaka
Control and Data Flow Visualization for Parallel Logic Programs on a Multi-window Debugger HyperDEBU. PARLE (1993)
Kentaro Shimada, Hanpei Koike, Hidehiko Tanaka
The Instruction Set Architecture of the Inference Processor UNIRED II. Architectures and Compilation Techniques for Fine and Medium Grain Parallelism (1993)
Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka
Architecture of Parallel Management Kernel for PIE64. PARLE (1992)
Kentaro Shimada, Hanpei Koike, Hidehiko Tanaka
UNIRED II: The High Performance Inference Processor for the Parallel Inference Machine PIE64. FGCS (1992)
Jun'ichi Tatemura, Hanpei Koike, Hidehiko Tanaka
HyperDEBU: A Multiwindow Debugger for Parallel Logic Programs. Programming Environments for Parallel Computing (1992)
Yasuo Hidaka, Hanpei Koike, Jun'ichi Tatemura, Hidehiko Tanaka
A Static Load Partitioning Method based on Execution Profile for Committed Choice Languages. ISLP (1991)
Lu Xu, Hanpei Koike, Hidehiko Tanaka
Distributed Garbage Collection for the Parallel Inference Machine PIE64. IFIP Congress (1989)
Lu Xu, Hanpei Koike, Hidehiko Tanaka
Distributed Garbage Collection for the Parallel Inference Engine PIE64. NACLP (1989)
Hanpei Koike, Hidehiko Tanaka
Multi-Context Processing and Data Balancing Mechanism of the Parallel Inference Machine PIE64. FGCS (1988)
Hanpei Koike, Hidehiko Tanaka
Fast Execution Mechanisms of Parallel Inference Engine PIE: PIEpelined Goal Rewriting and Goal Multicasting. LP (1986)