Yasuo Hidaka

Publication Activity (10 Years)

Years Active: 1991-2013
Publications (10 Years): 0

Top Topics

Subband Decomposition

Top Venues

IEEE J. Solid State Circuits

Publications

Yuuki Ogata, Yasuo Hidaka, Yoichi Koyanagi, Sadanori Akiya, Yuji Terao, Kosuke Suzuki, Keisuke Kashiwa, Masanobu Suzuki, Hirotaka Tamura
32Gb/s 28nm CMOS time-interleaved transmitter compatible with NRZ receiver with DFE. ISSCC (2013)
Yue Lu, Kwangmo Jung, Yasuo Hidaka, Elad Alon
Design and Analysis of Energy-Efficient Reconfigurable Pre-Emphasis Voltage-Mode Transmitters. IEEE J. Solid State Circuits 48 (8) (2013)
Samir Parikh, Tony Kao, Yasuo Hidaka, Jian Jiang, Asako Toda, Scott McLeod, William W. Walker, Yoichi Koyanagi, Toshiyuki Shibuya, Jun Yamada
A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS. ISSCC (2013)
Yue Lu, Kwangmo Jung, Yasuo Hidaka, Elad Alon
A 10Gb/s 10mW 2-tap reconfigurable pre-emphasis transmitter in 65nm LP CMOS. CICC (2012)
Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Takashi Miyoshi, Hideki Osone, Samir Parikh, Subodh M. Reddy, Toshiyuki Shibuya, Yasushi Umezawa, William W. Walker
A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel. ISSCC (2011)
Yasuo Hidaka, Weixin Gai, Takeshi Horie, Jian Hong Jiang, Yoichi Koyanagi, Hideki Osone
A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control. ISSCC (2009)
Yasuo Hidaka, Weixin Gai, Takeshi Horie, Jian Hong Jiang, Yoichi Koyanagi, Hideki Osone
A 4-Channel 1.25-10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control. IEEE J. Solid State Circuits 44 (12) (2009)
Jian Hong Jiang, Weixin Gai, Akira Hattori, Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Hideki Osone
Design Consideration of 6.25 Gbps Signaling for High-Performance Server. ASP-DAC (2007)
Yasuo Hidaka, Weixin Gai, Akira Hattori, Takeshi Horie, Jian Jiang, Kouichi Kanda, Yoichi Koyanagi, Satoshi Matsubara, Hideki Osone
A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer. ISSCC (2007)
Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka
Architecture of parallel management kernel for PIE64. Future Gener. Comput. Syst. 10 (1) (1994)
Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka
Multiple Threads in Cyclic Register Windows. ISCA (1993)
Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka
Architecture of Parallel Management Kernel for PIE64. PARLE (1992)
Yasuo Hidaka, Hanpei Koike, Jun'ichi Tatemura, Hidehiko Tanaka
A Static Load Partitioning Method based on Execution Profile for Committed Choice Languages. ISLP (1991)