Toshiyuki Shibuya

Publication Activity (10 Years)

Years Active: 1990-2019
Publications (10 Years): 2

Top Topics

Silicon On Insulator

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Toshiyuki Shibuya
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2019)
Toshiyuki Shibuya
Conference Reports: Recap of the 24th Asia and South Pacific Design Automation Conference. IEEE Des. Test 36 (4) (2019)
Samir Parikh, Tony Kao, Yasuo Hidaka, Jian Jiang, Asako Toda, Scott McLeod, William W. Walker, Yoichi Koyanagi, Toshiyuki Shibuya, Jun Yamada
A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS. ISSCC (2013)
Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Takashi Miyoshi, Hideki Osone, Samir Parikh, Subodh M. Reddy, Toshiyuki Shibuya, Yasushi Umezawa, William W. Walker
A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel. ISSCC (2011)
Lijuan Luo, Tan Yan, Qiang Ma, Martin D. F. Wong, Toshiyuki Shibuya
A New Strategy for Simultaneous Escape Based on Boundary Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (2) (2011)
Izumi Nitta, Yuji Kanazawa, Daisuke Fukuda, Toshiyuki Shibuya, Naoki Idani, Masaru Ito, Osamu Yamasaki, Norihiro Harada, Takanori Hiramoto
"Condition-based" dummy fill insertion method based on ECP and CMP predictive models. ISQED (2010)
Lijuan Luo, Tan Yan, Qiang Ma, Martin D. F. Wong, Toshiyuki Shibuya
B-escape: a simultaneous escape routing algorithm based on boundary routing. ISPD (2010)
Yu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Shibuya, Yuzi Kanazawa
Generation of yield-embedded Pareto-front for simultaneous optimization of yield and performances. DAC (2010)
Yu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Shibuya
Find the 'Best' Solution from Multiple Analog Topologies via Pareto-Optimality. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Yu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Shibuya
Efficiently finding the 'best' solution with multi-objectives from multiple topologies in topology library of analog circuit. ASP-DAC (2009)
Wanping Zhang, Wenjian Yu, Xiang Hu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng
Efficient Power Network Analysis Considering Multidomain Clock Gating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (9) (2009)
Katsumi Homma, Izumi Nitta, Toshiyuki Shibuya
Non-Gaussian Statistical Timing models of die-to-die and within-die parameter variations for full chip analysis. ASP-DAC (2008)
Wanping Zhang, Yi Zhu, Wenjian Yu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Nuriyoki Ito, Chung-Kuan Cheng
Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network. DATE (2008)
Wanping Zhang, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng
Fast power network analysis with multiple clock domains. ICCD (2007)
Chung-Kuan Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen
Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies? ASP-DAC (2005)
Toshiyuki Shibuya, Rajeev Murgai, Tadashi Konno, Kazuhiro Emi, Kaoru Kawamura
PDL: A New Physical Synthesis Methodology. ISQED (2003)
Jason Cong, Honching Peter Li, Sung Kyu Lim, Toshiyuki Shibuya, Dongmin Xu
Large scale circuit partitioning with loose/stable net removal and signal flow based clustering. ICCAD (1997)
Kaoru Kawamura, Tatsuya Shindo, Toshiyuki Shibuya, Hideki Miwatari, Yoshie Ohki
Touch and Cross Router. ICCAD (1990)