Roberto Suaya

Publication Activity (10 Years)

Years Active: 1990-2019
Publications (10 Years): 1

Top Topics

Geometric Properties

Wavelet Decomposition

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Guillermo H. Makar, Francisco J. Badenas, Roberto G. Simone, Alejandro Furfaro, Kenneth S. Stevens, Roberto Suaya
Low Power SPI Design Based on Relative Timing Techniques. ICECS (2019)
Shomit Das, Georgios Manetas, Kenneth S. Stevens, Roberto Suaya
Leveraging the geometric properties of on-chip transmission line structures to improve interconnect performance: A case study in 65nm. NOCS (2013)
Zohaib Mahmood, Roberto Suaya, Luca Daniel
An efficient framework for passive compact dynamical modeling of multiport linear systems. DATE (2012)
Chuan Xu, Navin Srivastava, Roberto Suaya, Kaustav Banerjee
Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs With Multiple Substrates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (11) (2012)
Navin Srivastava, Roberto Suaya, Kaustav Banerjee
Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate. DATE (2010)
Navin Srivastava, Chuan Xu, Roberto Suaya, Kaustav Banerjee
Corrections to "Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate" [Jul 09 1047-1060]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (5) (2010)
Navin Srivastava, Roberto Suaya, Kaustav Banerjee
Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (7) (2009)
Navin Srivastava, Roberto Suaya, Kaustav Banerjee
High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate. DATE (2008)
Salvador Ortiz, Roberto Suaya
Efficient implementation of conduction modes for modelling skin effect. ISVLSI (2007)
Rafael Escovar, Salvador Ortiz, Roberto Suaya
Mutual inductance between intentional inductors: closed form expressions. ISCAS (2006)
Salvador Ortiz, Roberto Suaya
Fullwave volumetric Maxwell solver using conduction modes. ICCAD (2006)
Rafael Escovar, Salvador Ortiz, Roberto Suaya
An improved long distance treatment for mutual inductance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (5) (2005)
Chung-Kuan Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen
Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies? ASP-DAC (2005)
Rafael Escovar, Salvador Ortiz, Roberto Suaya
Mutual inductance extraction and the dipole approximation. ISPD (2004)
Rafael Escovar, Roberto Suaya
Optimal design of clock trees for multigigahertz applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (3) (2004)
Rafael Escovar, Roberto Suaya
Transmission line design of clock trees. ICCAD (2002)
Paul de Dood, John Wawrzynek, Erwin Liu, Roberto Suaya
A Two-Dimensional Topological Compactor With Octagonal Geometry. DAC (1991)
Jeffrey Joyce, Erwin Liu, John M. Rushby, Natarajan Shankar, Roberto Suaya, Friedrich W. von Henke
From formal verification to silicon compilation. Compcon (1991)
John Valainis, Sinan Kaptanoglu, Erwin Liu, Roberto Suaya
Two-dimensional IC layout compaction based on topological design rule checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 (3) (1990)