Low Power SPI Design Based on Relative Timing Techniques.
Guillermo H. MakarFrancisco J. BadenasRoberto G. SimoneAlejandro FurfaroKenneth S. StevensRoberto SuayaPublished in: ICECS (2019)
Keyphrases
- low power
- single chip
- power consumption
- low cost
- logic circuits
- high speed
- low power consumption
- vlsi architecture
- cmos image sensor
- power dissipation
- power reduction
- design process
- mixed signal
- digital signal processing
- vlsi circuits
- gate array
- wireless transmission
- cmos technology
- signal processing
- delay insensitive
- nm technology