Navin Srivastava

Publication Activity (10 Years)

Years Active: 2005-2012
Publications (10 Years): 0

Top Topics

Wavelet Decomposition

Multiresolution

High Frequencies

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Chuan Xu, Navin Srivastava, Roberto Suaya, Kaustav Banerjee
Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs With Multiple Substrates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (11) (2012)
Navin Srivastava, Roberto Suaya, Kaustav Banerjee
Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate. DATE (2010)
Navin Srivastava, Chuan Xu, Roberto Suaya, Kaustav Banerjee
Corrections to "Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate" [Jul 09 1047-1060]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (5) (2010)
Navin Srivastava, Roberto Suaya, Kaustav Banerjee
Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (7) (2009)
Navin Srivastava, Roberto Suaya, Kaustav Banerjee
High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate. DATE (2008)
Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood
3D Integration for Introspection. IEEE Micro 27 (1) (2007)
Kaustav Banerjee, Sheng-Chih Lin, Navin Srivastava
Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems. ASP-DAC (2006)
Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood, Kaustav Banerjee
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy. DAC (2006)
Kaustav Banerjee, Sungjun Im, Navin Srivastava
Can Carbon Nanotubes Extend the Lifetime of On-Chip Electrical Interconnections? Nano-Net (2006)
Kaustav Banerjee, Navin Srivastava
Are carbon nanotubes the future of VLSI interconnections? DAC (2006)
Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood
Introspective 3D chips. ASPLOS (2006)
Navin Srivastava, Kaustav Banerjee
Performance analysis of carbon nanotube interconnects for VLSI applications. ICCAD (2005)
Navin Srivastava, Xiaoning Qi, Kaustav Banerjee
Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits. ISQED (2005)
Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee
A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs. ICCD (2005)