Hideki Osone

Publication Activity (10 Years)

Years Active: 1995-2011
Publications (10 Years): 0

Publications

Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Takashi Miyoshi, Hideki Osone, Samir Parikh, Subodh M. Reddy, Toshiyuki Shibuya, Yasushi Umezawa, William W. Walker
A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel. ISSCC (2011)
Yasuo Hidaka, Weixin Gai, Takeshi Horie, Jian Hong Jiang, Yoichi Koyanagi, Hideki Osone
A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control. ISSCC (2009)
Yasuo Hidaka, Weixin Gai, Takeshi Horie, Jian Hong Jiang, Yoichi Koyanagi, Hideki Osone
A 4-Channel 1.25-10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control. IEEE J. Solid State Circuits 44 (12) (2009)
Jian Hong Jiang, Weixin Gai, Akira Hattori, Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Hideki Osone
Design Consideration of 6.25 Gbps Signaling for High-Performance Server. ASP-DAC (2007)
Yasuo Hidaka, Weixin Gai, Akira Hattori, Takeshi Horie, Jian Jiang, Kouichi Kanda, Yoichi Koyanagi, Satoshi Matsubara, Hideki Osone
A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer. ISSCC (2007)
Nirmal R. Saxena, Chien Chen, Ravi Swami, Hideki Osone, Shalesh Thusoo, David Lyon, David Chang, Anand Dharmaraj, Niteen Patkar, Yizhi Lu, Ben Chia
Error Detection and Handling in a Superscalar, Speculative Out-of-Order Execution Processor System. FTCS (1995)