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Masato Yoshioka
Publication Activity (10 Years)
Years Active: 2007-2014
Publications (10 Years): 0
Top Topics
Nm Technology
Power Management
Sigma Delta
Cmos Image Sensor
Top Venues
VLSI-DAT
IEEE J. Solid State Circuits
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Publications
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Takumi Danjo
,
Masato Yoshioka
,
Masayuki Isogai
,
Masanori Hoshino
,
Sanroku Tsukamoto
A 6-bit, 1-GS/s, 9.9-mW, Interpolated Subranging ADC in 65-nm CMOS.
IEEE J. Solid State Circuits
49 (3) (2014)
Takumi Danjo
,
Masato Yoshioka
,
Masayuki Isogai
,
Masanori Hoshino
,
Sanroku Tsukamoto
A 6b, 1GS/s, 9.9mW interpolated subranging ADC in 65nm CMOS.
VLSI-DAT
(2012)
Yanfei Chen
,
Xiaolei Zhu
,
Hirotaka Tamura
,
Masaya Kibune
,
Yasumoto Tomita
,
Takayuki Hamada
,
Masato Yoshioka
,
Kiyoshi Ishikawa
,
Takeshi Takayama
,
Junji Ogawa
,
Sanroku Tsukamoto
,
Tadahiro Kuroda
Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC.
IEICE Trans. Electron.
(3) (2010)
Masato Yoshioka
,
Kiyoshi Ishikawa
,
Takeshi Takayama
,
Sanroku Tsukamoto
A 10b 50MS/s 820µW SAR ADC with on-chip digital calibration.
ISSCC
(2010)
Yu Liu
,
Masato Yoshioka
,
Katsumi Homma
,
Toshiyuki Shibuya
,
Yuzi Kanazawa
Generation of yield-embedded Pareto-front for simultaneous optimization of yield and performances.
DAC
(2010)
Masato Yoshioka
,
Kiyoshi Ishikawa
,
Takeshi Takayama
,
Sanroku Tsukamoto
A 10-b 50-MS/s 820- μ W SAR ADC With On-Chip Digital Calibration.
IEEE Trans. Biomed. Circuits Syst.
4 (6) (2010)
Yu Liu
,
Masato Yoshioka
,
Katsumi Homma
,
Toshiyuki Shibuya
Find the 'Best' Solution from Multiple Analog Topologies via Pareto-Optimality.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(12) (2009)
Yanfei Chen
,
Xiaolei Zhu
,
Hirotaka Tamura
,
Masaya Kibune
,
Yasumoto Tomita
,
Takayuki Hamada
,
Masato Yoshioka
,
Kiyoshi Ishikawa
,
Takeshi Takayama
,
Junji Ogawa
,
Sanroku Tsukamoto
,
Tadahiro Kuroda
Split capacitor DAC mismatch calibration in successive approximation ADC.
CICC
(2009)
Yu Liu
,
Masato Yoshioka
,
Katsumi Homma
,
Toshiyuki Shibuya
Efficiently finding the 'best' solution with multi-objectives from multiple topologies in topology library of analog circuit.
ASP-DAC
(2009)
Masato Yoshioka
,
Masahiro Kudo
,
Toshihiko Mori
,
Sanroku Tsukamoto
A 0.8V 10b 8OMS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing.
ISSCC
(2007)