A 10b 50MS/s 820µW SAR ADC with on-chip digital calibration.

Masato Yoshioka Kiyoshi Ishikawa Takeshi Takayama Sanroku Tsukamoto

Published in: ISSCC (2010)

Keyphrases

sigma delta
analog to digital converter
circuit design
mixed signal
single chip
phase locked loop
low power
synthetic aperture radar
cmos image sensor
high speed
camera calibration
high density
parameter estimation
automatic target recognition
low cost
intrinsic parameters
analog vlsi
computer vision
multiresolution