Shuichi Sakai

ORCID

Publication Activity (10 Years)

Years Active: 1985-2024
Publications (10 Years): 39

Top Venues

ICCD

IEICE Trans. Inf. Syst.

MCSoC

SenSys

Publications

Reoma Matsuo, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
Branch Divergence-Aware Flexible Approximating Technique on GPUs. COOL CHIPS (2024)
Shun Nagasaki, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Multi-Tree Network Protocol Enabling System Partitioning for Shape-Changeable Computer System. CF (2024)
Masato Goto, Ibuki Sugiyama, Kenta Higuchi, Toshiki Goto, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
CommuTiles: Shape-Changeable Modular Computer System Using Proximity Wireless Communication. CHI Extended Abstracts (2024)
Takashi Murayama, Shu Sugita, Hiroyuki Saegusa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
iKnowde: Interactive Learning Path Generation System Based on Knowledge Dependency Graphs. UIST (Adjunct Volume) (2023)
Shun Nagasaki, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Dynamically Reconfigurable Network Protocol for Shape-Changeable Computer System. IEEE Des. Test 40 (6) (2023)
Yusuke Izawa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
A Functional Reactive Programming Language for Wirelessly Connected Shape-Changeable Chiplet-Based Computers. SPLASH Companion (2023)
Reoma Matsuo, Toru Koizumi, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
TURBULENCE: Complexity-effective Out-of-order Execution on GPU with Distance-based ISA. DATE (2023)
Kenta Higuchi, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Poster Abstract: Investigation of Distance Sensing Method Using Magnetic Resonant Coupled Coils for Deformable User Interfaces. SenSys (2023)
Toru Koizumi, Ryota Shioya, Shu Sugita, Taichi Amano, Yuya Degawa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Clockhands: Rename-free Instruction Set Architecture for Out-of-order Processors. MICRO (2023)
Taichi Amano, Junichiro Kadomoto, Satoshi Mitsuno, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
An Out-of-Order Superscalar Processor Using STRAIGHT Architecture in 28 nm CMOS. ISCAS (2023)
Shu Sugita, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
A Sound and Complete Algorithm for Code Generation in Distance-Based ISA. CC (2023)
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Poster Abstract: Towards a Tiny Digital Displacement Sensor Utilizing Bit-Error Characteristics of Inter-Chip Wireless Bus. SenSys (2023)
Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
A Principal Factor of Performance in Decoupled Front-End. IEICE Trans. Inf. Syst. 106 (12) (2023)
Rin Oishi, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
FPGA-based Garbling Accelerator with Parallel Pipeline Processing. IEICE Trans. Inf. Syst. 106 (12) (2023)
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Evaluation of Different Microarchitectures for Energy-Efficient RISC-V Cores. MCSoC (2022)
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Deformable Chiplet-Based Computer Using Inductively Coupled Wireless Communication. ASP-DAC (2022)
Toru Koizumi, Tomoki Nakamura, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
T-SKID: Predicting When to Prefetch Separately from Address Prediction. DATE (2022)
Tomoki Nakamura, Kazutaka Tomida, Shouta Kouno, Hidetsugu Irie, Shuichi Sakai
Stochastic Iterative Approximation: Software/hardware techniques for adjusting aggressiveness of approximation. ICCD (2021)
Toru Koizumi, Shu Sugita, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Compiling and Optimizing Real-world Programs for STRAIGHT ISA. ICCD (2021)
Junichiro Kadomoto, Takuya Sasatani, Koya Narumi, Naoto Usami, Hidetsugu Irie, Shuichi Sakai, Yoshihiro Kawahara
Toward Wirelessly Cooperated Shape-Changing Computing Particles. IEEE Pervasive Comput. 20 (3) (2021)
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Multiport Register File Design for High-Performance Embedded Cores. MCSoC (2021)
Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Accurate and Fast Performance Modeling of Processors with Decoupled Front-end. ICCD (2021)
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
A RISC-V Processor with an Inter-Chiplet Wireless Communication Interface for Shape-Changeable Computers. COOL CHIPS (2020)
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
A Self-Sensing Technique Using Inductively-Coupled Coils for Deformable User Interfaces. AsianCHI@CHI (2020)
Satoshi Mitsuno, Junichiro Kadomoto, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
A High-Performance Out-of-Order Soft Processor Without Register Renaming. FPL (2020)
Junichiro Kadomoto, Satoshi Mitsuno, Hidetsugu Irie, Shuichi Sakai
An Inductively Coupled Wireless Bus for Chiplet-Based Systems. ASP-DAC (2020)
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Design of Shape-Changeable Chiplet-Based Computers Using an Inductively Coupled Wireless Bus Interface. ICCD (2020)
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
WiXI: An Inter-Chip Wireless Bus Interface for Shape-Changeable Chiplet-Based Computers. ICCD (2019)
Takahiro Yamada, Hidetsugu Irie, Masahiro Kunitake, Eiji Nagano, Shuichi Sakai
Estimating driver's readiness by understanding driving posture. ICCE (2018)
Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai
Bank-Aware Instruction Scheduler for a Multibanked Register File. J. Inf. Process. 26 (2018)
Toru Koizumi, Satoshi Nakae, Akifumi Fukuda, Hidetsugu Irie, Shuichi Sakai
Reduction of Instruction Increase Overhead by STRAIGHT Compiler. CANDAR Workshops (2018)
Hidetsugu Irie, Toru Koizumi, Akifumi Fukuda, Seiya Akaki, Satoshi Nakae, Yutaro Bessho, Ryota Shioya, Takahiro Notsu, Katsuhiro Yoda, Teruo Ishihara, Shuichi Sakai
STRAIGHT: Hazardless Processor Architecture Without Register Renaming. MICRO (2018)
Junichiro Kadomoto, Toru Koizumi, Akifumi Fukuda, Reoma Matsuo, Susumu Mashimo, Akifumi Fujita, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
An Area-Efficient Out-of-Order Soft-Core Processor Without Register Renaming. FPT (2018)
Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai
Skewed Multistaged Multibanked Register File for Area and Energy Efficiency. IEICE Trans. Inf. Syst. (4) (2017)
Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai
Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology. IEICE Trans. Electron. (3) (2017)
Mizuki Miyanaga, Hidetsugu Irie, Shuichi Sakai
Accelerating Integrity Verification on Secure Processors by Promissory Hash. PRDC (2017)
Takahiro Yamada, Hidetsugu Irie, Shuichi Sakai
High-Accuracy Joint Position Estimation and Posture Detection System for Driving. MobiQuitous (Adjunct Proceedings) (2016)
Hayato Nomura, Hiroyuki Katchi, Hidetsugu Irie, Shuichi Sakai
"Stubborn" strategy to mitigate remaining cache misses. ICCD (2016)
Minseong Choi, Takashi Fukuda, Masahiro Goshima, Shuichi Sakai
An Inductive Method to Select Simulation Points. IEICE Trans. Inf. Syst. (12) (2016)
Naruki Kurata, Ryota Shioya, Masahiro Goshima, Shuichi Sakai
Address Order Violation Detection with Parallel Counting Bloom Filters. IEICE Trans. Electron. (7) (2015)
Minseong Choi, Takashi Fukuda, Masahiro Goshima, Shuichi Sakai
An Inductive Method to Select Simulation Points. CANDAR (2015)
Koki Murakami, Tsuyoshi Yamada, Rie Shigetomi Yamaguchi, Masahiro Goshima, Shuichi Sakai
A cloud architecture for protecting guest's information from malicious operators with memory management. CODASPY (2014)
Ryota Shioya, Naruki Kurata, Takashi Toyoshima, Masahiro Goshima, Shuichi Sakai
Register Indirect Jump Target Forwarding. IEICE Trans. Inf. Syst. (2) (2013)
Ryota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, Shuichi Sakai
Low-Overhead Architecture for Security Tag. IEICE Trans. Inf. Syst. (1) (2011)
Ryota Shioya, Kazuo Horio, Masahiro Goshima, Shuichi Sakai
Register Cache System Not for Latency Reduction Purpose. MICRO (2010)
Ryota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, Shuichi Sakai
Low-Overhead Architecture for Security Tag. PRDC (2009)
Shuichi Sakai, Hidetoshi Onodera, Hiroto Yasuura, James C. Hoe
Dependable VLSI: device, design and architecture: how should they cooperate? ASP-DAC (2009)
Kunbo Li, Ryota Shioya, Masahiro Goshima, Shuichi Sakai
String-Wise Information Flow Tracking against Script Injection Attacks. PRDC (2009)
Shuichi Sakai, Masahiro Goshima, Hidetsugu Irie
Ultra Dependable Processor. IEICE Trans. Electron. (9) (2008)
Hidetsugu Irie, Ken Sugimoto, Masahiro Goshima, Shuichi Sakai
Preventing timing errors on register writes: mechanisms of detections and recoveries. SIGARCH Comput. Archit. News 35 (5) (2007)
Tomoyoshi Kinoshita, Ibuki Handa, Makoto Muto, Shuichi Sakai, Hidehiko Tanaka
Musical part separation based on perceptual hierarchy. Systems and Computers in Japan 38 (2) (2007)
Luong Dinh Hung, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai
Utilization of SECDED for soft error and variation-induced defect tolerance in caches. DATE (2007)
Naoya Hatta, Niko Demus Barli, Chitaka Iwama, Luong Dinh Hung, Daisuke Tashiro, Shuichi Sakai, Hidehiko Tanaka
Bus Serialization for Reducing Power Consumption. Inf. Media Technol. 1 (2) (2006)
Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai
SEVA: A Soft-Error- and Variation-Aware Cache Architecture. PRDC (2006)
Satoshi Katsunuma, Hiroyuki Kurita, Ryota Shioya, Kazuto Shimizu, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai
Base Address Recognition with Data Flow Tracking for Injection Attack Detection. PRDC (2006)
Luong Dinh Hung, Shuichi Sakai
Dynamic Estimation of Task Level Parallelism with Operating System Support. Inf. Media Technol. 1 (2) (2006)
Koichi Miura, Motomu Takano, Reiko Hamada, Ichiro Ide, Shuichi Sakai, Hidehiko Tanaka
Associating semantically structured cooking videos with their preparation steps. Systems and Computers in Japan 36 (2) (2005)
Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai
Mitigating Soft Errors in Highly Associative Cache with CAM-based Tag. ICCD (2005)
Luong Dinh Hung, Shuichi Sakai
Dynamic Estimation of Task Level Parallelism with Operating System Support. ISPAN (2005)
Reiko Hamada, Jun Okabe, Ichiro Ide, Shin'ichi Satoh, Shuichi Sakai, Hidehiko Tanaka
Cooking navi: assistant for daily cooking in kitchen. ACM Multimedia (2005)
Reiko Hamada, Koichi Miura, Ichiro Ide, Shin'ichi Satoh, Shuichi Sakai, Hidehiko Tanaka
Multimedia Integration for Cooking Video Indexing. PCM (2) (2004)
Hideyuki Miura, Luong Dinh Hung, Chitaka Iwama, Daisuke Tashiro, Niko Demus Barli, Shuichi Sakai, Hidehiko Tanaka
Compiler-Assisted Thread Level Control Speculation. Euro-Par (2003)
Yoshimitsu Yanagawa, Luong Dinh Hung, Chitaka Iwama, Niko Demus Barli, Shuichi Sakai, Hidehiko Tanaka
Complexity Analysis of a Cache Controller for Speculative Multithreading Chip Multiprocessors. HiPC (2003)
Koichi Miura, Reiko Hamada, Ichiro Ide, Shuichi Sakai, Hidehiko Tanaka
Associating Cooking Video Segments with Preparation Steps. CIVR (2003)
Ichiro Ide, Reiko Hamada, Shuichi Sakai, Hidehiko Tanaka
Compilation of dictionaries for semantic attribute analysis of television news captions. Systems and Computers in Japan 34 (12) (2003)
Shuichi Sakai, Mitsunori Togasaki, Koichi Yamazaki
A note on greedy algorithms for the maximum weighted independent set problem. Discret. Appl. Math. 126 (2-3) (2003)
Okihisa Utsumi, Koichi Miura, Ichiro Ide, Shuichi Sakai, Hidehiko Tanaka
An object detection method for describing soccer games from video. ICME (1) (2002)
Shuichi Sakai
CMP on SoC: Architect's View. ISSS (2002)
Chitaka Iwama, Niko Demus Barli, Shuichi Sakai, Hidehiko Tanaka
Improving Conditional Branch Prediction on Speculative Multithreading Architectures. Euro-Par (2001)
Ichiro Ide, Reiko Hamada, Shuichi Sakai, Hidehiko Tanaka
An attribute based news video indexing. ACM Multimedia Workshops (2001)
Reiko Hamada, Ichiro Ide, Shuichi Sakai, Hidehiko Tanaka
Structural analysis of cooking preparation steps in Japanese. IRAL (2000)
Ichiro Ide, Reiko Hamada, Shuichi Sakai, Hidehiko Tanaka
Scene identification in news video by character region segmentation. ACM Multimedia Workshops (2000)
Reiko Hamada, Ichiro Ide, Shuichi Sakai
Associating cooking video with related textbook. ACM Multimedia Workshops (2000)
Ichiro Ide, Reiko Hamada, Shuichi Sakai, Hidehiko Tanaka
Relating Graphical Features with Concept Classes for Automatic News Video Indexing. Intelligent Information Integration (1999)
Reiko Hamada, Ichiro Ide, Shuichi Sakai, Hidehiko Tanaka
Associating video with related documents. ACM Multimedia (2) (1999)
Masaaki Honda, Takeo Igarashi, Hidehiko Tanaka, Shuichi Sakai
Integrated Manipulation: Context-Aware Manipulation of 2D Diagrams. ACM Symposium on User Interface Software and Technology (1999)
Antonio Magnaghi, Shuichi Sakai, Hidehiko Tanaka
Inter-procedural Analysis for Parallelization of Java Programs. ACPC (1999)
Andrew Sohn, Yuetsu Kodama, Jui Ku, Mitsuhisa Sato, Hirofumi Sakane, Hayato Yamana, Shuichi Sakai, Yoshinori Yamaguchi
Fine-Grain Multithreading with the EM-X Multiprocessor. SPAA (1997)
Takashi Yokota, Hiroshi Matsuoka, Kazuaki Okamoto, Hideo Hirono, Shuichi Sakai
Virtual control channel and its application to the massively parallel computer RWC-1. HiPC (1997)
Mitsuhisa Sato, Yuetsu Kodama, Hirofumi Sakane, Hayato Yamana, Shuichi Sakai, Yoshinori Yamaguchi
Experience with Fine-Grain Communication in EM-X Multiprocessor for Parallel Sparse Matrix Computation. IPPS (1997)
Yuetsu Kodama, Hirofumi Sakane, Hanpei Koike, Mitsuhisa Sato, Shuichi Sakai, Yoshinori Yamaguchi
Parallel Execution of Radix Sort Program Using Fine-Grain Communication. IEEE PACT (1997)
Andrew Sohn, Jui Ku, Yuetsu Kodama, Mitsuhisa Sato, Hirofumi Sakane, Hayato Yamana, Shuichi Sakai, Yoshinori Yamaguchi
Identifying the capability of overlapping computation with communication. IEEE PACT (1996)
Kazuaki Okamoto, Shuichi Sakai, Hiroshi Matsuoka, Takashi Yokota, Hideo Hirono
Multithread execution mechanisms on RICA-1 for massively parallel computation. IEEE PACT (1996)
Hayato Yamana, Mitsuhisa Sato, Yuetsu Kodama, Hirofumi Sakane, Shuichi Sakai, Yoshinori Yamaguchi
A Macrotask-level Unlimited Speculative Execution on Multiprocessors. International Conference on Supercomputing (1995)
Shuichi Sakai, Yuetsu Kodama, Mitsuhisa Sato, Andrew Shaw, Hiroshi Matsuoka, Hideo Hirono, Kazuaki Okamoto, Takashi Yokota
Reduced Interprocessor-Communication Architecture and its Implementation on EM-4. Parallel Comput. 21 (5) (1995)
Yuetsu Kodama, Hirohumi Sakane, Mitsuhisa Sato, Hayato Yamana, Shuichi Sakai, Yoshinori Yamaguchi
The EM-X Parallel Computer: Architecture and Basic Performance. ISCA (1995)
Atsushi Hori, Takashi Yokota, Yutaka Ishikawa, Shuichi Sakai, Hiroki Konaka, Munenori Maeda, Takashi Tomokiyo, Jörg Nolte, Hiroshi Matsuoka, Kazuaki Okamoto, Hideo Hirono
Time Space Sharing Scheduling and Architectural Support. JSSPP (1995)
Takashi Yokota, Hiroshi Matsuoka, Kazuaki Okamoto, Hideo Hirono, Atsushi Hori, Shuichi Sakai
A prototype router for the massively parallel computer RWC-1. ICCD (1995)
Yuetsu Kodama, Hirofumi Sakane, Mitsuhisa Sato, Shuichi Sakai, Yoshinori Yamaguchi
Message-based efficient remote memory access on a highly parallel computer EM-X. ISPAN (1994)
Andrew Sohn, Mitsuhisa Sato, Shuichi Sakai, Yuetsu Kodama, Yoshinori Yamaguchi
Nonnumeric search results on the EM-4 distributed-memory multiprocessor. SC (1994)
Andrew Sohn, Mitsuhisa Sato, Shuichi Sakai, Yuetsu Kodama, Yoshinori Yamaguchi
Parallel bidirectional heuristic search on the EM-4 multiprocessor. SPDP (1994)
Mitsuhisa Sato, Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi
EM-C: Programming with Explicit Parallelism and Locality for EM-4 Multiprocessor. IFIP PACT (1994)
Shuichi Sakai
Overview of RWC Massively Parallel Computer Project. HPDC (1994)
Mitsuhisa Sato, Yuetsu Kodama, Yoshinori Yamaguchi, Shuichi Sakai
Experience with Executing Shared Memory Programs using Fine-Grain Communication and Multithreading in EM-4. IPPS (1994)
Mitsuhisa Sato, Yuetsu Kodama, Hirofumi Sakane, Yoshinori Yamaguchi, Shuichi Sakai
Programming with Distributed Data Structure for EM-X Multiprocessor. Theory and Practice of Parallel Programming (1994)
Shuichi Sakai, Kazuaki Okamoto, Hiroshi Matsuoka, Hideo Hirono, Yuetsu Kodama, Mitsuhisa Sato
Super-Threading: Architectural and Software Mechanisms for Optimizing Parallel Computation. International Conference on Supercomputing (1993)
Shuichi Sakai, Hiroshi Matsuoka, Yuetsu Kodama, Mitsuhisa Sato, Andrew Shaw, Hideo Hirono, Kazuaki Okamoto, Takashi Yokota
RICA: Reduced Interprocessor-Communication Architecture - Concept and Mechanisms. SPDP (1993)
Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi
Evaluation of parallel execution performance by highly parallel computer EM-4. Systems and Computers in Japan 24 (9) (1993)
Shuichi Sakai, Yuetsu Kodama, Yoshinori Yamaguchi
Design and Implementation of a Circular Omega Network in the EM-4. Parallel Comput. 19 (2) (1993)
Yuetsu Kodama, Yasuhito Koumura, Mitsuhisa Sato, Hirohumi Sakane, Shuichi Sakai, Yoshinori Yamaguchi
EMC-Y: Parallel Processing Element Optimizing Communication and Computation. International Conference on Supercomputing (1993)

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Publication Activity (10 Years)

Top Topics

Top Venues

Shuichi Sakai