Takashi Yokota

Publication Activity (10 Years)

Years Active: 1986-2024
Publications (10 Years): 37

Top Topics

Parallel Processing

Top Venues

IEICE Trans. Inf. Syst.

Publications

Takeshi Ohkawa, Kenta Arai, Kanemitsu Ootsu, Takashi Yokota
Alchemist: A Component-Oriented Development Tool of FPGA based on Publish/Subscribe Model. ICCE (2024)
Takashi Yokota, Kanemitsu Ootsu, Shun Kojima
Enhancing Cup-Stacking Method for Collective Communication. IEICE Trans. Inf. Syst. 106 (11) (2023)
Tatsuya Tsuchiya, Kanemitsu Ootsu, Takashi Yokota, Shun Kojima
Assembly code translation from ARM64 to RISC-V. SNPD-Summer (2022)
Shun Kojima, Yi Feng, Kazuki Maruta, Kanemitsu Ootsu, Takashi Yokota, Chang-Jun Ahn, Vahid Tarokh
Towards Deep Learning-Guided Multiuser SNR and Doppler Shift Detection for Next-Generation Wireless Systems. VTC Spring (2022)
Jintaro Nogae, Kanemitsu Ootsu, Takashi Yokota, Shun Kojima
Comparison of reinforcement learning in game AI. SNPD-Summer (2022)
Takashi Yokota, Kanemitsu Ootsu, Shun Kojima
On a Cup-Stacking Concept in Repetitive Collective Communication. IEICE Trans. Inf. Syst. (7) (2022)
Yoshiki Kimura, Kanemitsu Ootsu, Tatsuya Tsuchiya, Takashi Yokota
Development of RISC-V Based Soft-core Processor with Scalable Vector Extension for Embedded System. ACIT (2021)
Shun Kojima, Yi Feng, Kazuki Maruta, Kanemitsu Ootsu, Takashi Yokota, Chang-Jun Ahn, Vahid Tarokh
Investigation of Input Signal Representation to CNN for Improving SNR Classification Accuracy. VTC Fall (2021)
Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa
Genetic Node-Mapping Methods for Rapid Collective Communications. IEICE Trans. Inf. Syst. (1) (2020)
Takashi Yokota, Kazunori Kojima, Shi-wook Lee, Yoshiaki Itoh
Reduction of Speech Data Posteriorgrams by Compressing Maximum-likelihood State Sequences in Query by Example. APSIPA (2020)
Tomoya Kikuchi, Yoshiki Kimura, Kanemitsu Ootsu, Takashi Yokota
Development of Soft-Core Processor with Efficient Array Data Transfer Mechanism. CANDAR (Workshops) (2020)
Takeshi Ohkawa, Kazushi Yamashina, Takuya Matsumoto, Kanemitsu Ootsu, Takashi Yokota
Automatic Generation Tool of FPGA Components for Robots. IEICE Trans. Inf. Syst. (5) (2019)
Takeshi Ohkawa, Yuhei Sugata, Harumi Watanabe, Nobuhiko Ogura, Kanemitsu Ootsu, Takashi Yokota
High level synthesis of ROS protocol interpretation and communication circuit for FPGA. RoSE@ICSE (2019)
Takanobu Baba, Shinpei Watanabe, Boaz Jessie Jackin, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota, Yoshio Hayasaki, Toyohiko Yatagai
Fast Computation with Efficient Object Data Distribution for Large-Scale Hologram Generation on a Multi-GPU Cluster. IEICE Trans. Inf. Syst. (7) (2019)
Kengo Jingu, Kohta Shigenobu, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota
Directive-Based Parallelization of For-Loops at LLVM IR Level. SNPD (2019)
Masahiro Nissato, Hiroki Sugiyama, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota
Realization and Preliminary Evaluation of MPI Runtime Environment on Android Cluster. AINA (2019)
Yoshiki Kimura, Tomoya Kikuchi, Kanemitsu Ootsu, Takashi Yokota
Proposal of Scalable Vector Extension for Embedded RISC-V Soft-Core Processor. CANDAR Workshops (2019)
Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa
Accelerating Large-Scale Interconnection Network Simulation by Cellular Automata Concept. IEICE Trans. Inf. Syst. (1) (2019)
Takanobu Baba, Shinpei Watanabe, Boaz Jessie Jackin, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota, Yoshio Hayasaki, Toyohiko Yatagai
Data Distribution Method for Fast Giga-scale Hologram Generation on a Multi-GPU Cluster. ApPLIED@PODC (2018)
Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa
A Genetic Approach for Accelerating Communication Performance by Node Mapping. IEICE Trans. Inf. Syst. (12) (2018)
Takanobu Baba, Shinpei Watanabe, Boaz Jessie Jackin, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota, Yoshio Hayasaki, Toyohiko Yatagai
Overcoming the difficulty of large-scale CGH generation on multi-GPU cluster. GPGPU@PPoPP (2018)
Hiromichi Wakatsuki, Takao Kido, Kenta Arai, Yuhei Sugata, Kanemitsu Ootsu, Takashi Yokota, Takeshi Ohkawa
Development of a Robot Car by Single Line Search Method for White Line Detection with FPGA. FPT (2018)
Takeshi Ohkawa, Kazushi Yamashina, Hitomi Kimura, Kanemitsu Ootsu, Takashi Yokota
FPGA Components for Integrating FPGAs into Robot Systems. IEICE Trans. Inf. Syst. (2) (2018)
Yuichi Nonaka, Daisuke Yoshida, Shogo Kitamura, Takashi Yokota, Madoka Hasegawa, Kanemitsu Ootsu
Monocular color-IR imaging system applicable for various light environments. ICCE (2018)
Kengo Jingu, Kohta Shigenobu, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota
An Implementation of LLVM Pass for Loop Parallelization Based on IR-Level Directives. CANDAR Workshops (2018)
Shinpei Watanabe, Boaz Jessie Jackin, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota, Yoshio Hayasaki, Toyohiko Yatagai, Takanobu Baba
Acceleration of Large-Scale CGH Generation Using Multi-GPU Cluster. CANDAR (2017)
Kohta Shigenobu, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota
A Translation Method of ARM Machine Code to LLVM-IR for Binary Code Parallelization and Optimization. CANDAR (2017)
Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa
A Static Packet Scheduling Approach for Fast Collective Communication by Using PSO. IEICE Trans. Inf. Syst. (12) (2017)
Yuichi Nonaka, Daisuke Yoshida, Takashi Yokota, Madoka Hasegawa, Kanemitsu Ootsu
Image Denoising Based on Human Visual Characteristics. ICAIP (2017)
Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota, Katsuya Kikuchi, Masahiro Aoyagi
Designing Efficient Parallel Processing in 3D Standard-Chip Stacking System with Standard Bus. MCSoC (2017)
Yuki Sawada, Yusuke Arai, Kanemitsu Ootsu, Takashi Yokota, Takeshi Ohkawa
Performance of Android Cluster System Allowing Dynamic Node Reconfiguration. Wirel. Pers. Commun. 93 (4) (2017)
Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa
Large-Scale Interconnection Network Simulation Methods Based on Cellular Automata. CANDAR (2017)
Yuhei Sugata, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota
Acceleration of Publish/Subscribe Messaging in ROS-compliant FPGA Component. HEART (2017)
Kazushi Yamashina, Hitomi Kimura, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota
cReComp: Automated Design Tool for ROS-Compliant FPGA Component. MCSoC (2016)
Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa
Enhancing Entropy Throttling: New Classes of Injection Control in Interconnection Networks. IEICE Trans. Inf. Syst. (12) (2016)
Takeshi Ohkawa, Kazushi Yamashina, Takuya Matsumoto, Kanemitsu Ootsu, Takashi Yokota
Architecture exploration of intelligent robot system using ros-compliant FPGA component. RSP (2016)
Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa
Introducing PSO for Optimal Packet Scheduling of Collective Communication. CANDAR (2016)
Kanemitsu Ootsu, Yutaka Matsuno, Takeshi Ohkawa, Takashi Yokota, Takanobu Baba
Empirical performance study of speculative parallel processing on commercial multi-core CPU with hardware transactional memory. SEPS@SPLASH (2015)
Yuki Sawada, Yusuke Arai, Kanemitsu Ootsu, Takashi Yokota, Takeshi Ohkawa
An Android cluster system capable of dynamic node reconfiguration. ICUFN (2015)
Hiroyuki Obuchi, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota
Efficient Translation and Execution Method for Automated Parallel Processing System by Using Valgrind. CANDAR (2015)
Kazushi Yamashina, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota
Proposal of ROS-compliant FPGA Component for Low-Power Robotic Systems. CoRR (2015)
Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa
Entropy Throttling: Towards Global Congestion Control of Interconnection Networks. CANDAR (2015)
Kosuke Hiraishi, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota
Proposal of Highly Efficient Memory Access Method Using Locked-Cache on Soft-Core Processor with SIMD Operations. CANDAR (2015)
Yuki Suzuki, Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa
Performance Improvement of Large-Scale Interconnection Network Simulator by Using GPU. CANDAR (2015)
Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa
Relaxing Heavy Congestion by State Propagation. J. Inf. Process. 23 (5) (2015)
Takeshi Ohkawa, Takashi Yokota, Kanemitsu Ootsu
A prototyping system for hardware distributed objects with diversity of programming languages design and preliminary evaluation. FPT (2013)
Hiroyoshi Jutori, Takanobu Baba, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota
Exploration of Highly Accurate Path Prediction Mechanism Using Detailed Path History. CANDAR (2013)
Takayuki Hoshi, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota
Runtime Overhead Reduction in Automated Parallel Processing System Using Valgrind. CANDAR (2013)
Masayuki Omote, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota
Efficient Data Communication Using Dynamic Switching of Compression Method. CANDAR (2013)
Yuanming Zhang, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba
An automatic thread decomposition approach for pipelined multithreading. Int. J. High Perform. Comput. Netw. 7 (3) (2013)
Takeshi Ohkawa, Daichi Uetake, Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba
Reconfigurable and hardwired ORB engine on FPGA by Java-to-HDL synthesizer for realtime application. SIGARCH Comput. Archit. News 41 (5) (2013)
Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa
A Cellular Automata Approach for Large-Scale Interconnection Network Simulation. CANDAR (2013)
Kazuhiro Kinkai, Takanobu Baba, Hiroyoshi Jutori, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota
Comparative Study of Path Prediction Method for Speculative Loop Execution. ICNC (2012)
Atsushi Shina, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota, Takanobu Baba
Proposal of Incremental Software Simulation for Reduction of Evaluation Time. ICNC (2012)
Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba
Steady/Unsteady Communication Performance in Large-Scale Regular Networks. AINA Workshops (2011)
Kanemitsu Ootsu, Takeshi Abe, Takashi Yokota, Takanobu Baba
Loop Performance Improvement for Min-cut Program Decomposition Method. ICNC (2010)
Yuanming Zhang, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba
Automatic Thread Decomposition for Pipelined Multithreading. ICPADS (2010)
Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba
An Effective Throttling Method Based on Quasi-global Congestion Information. ISPAN (2009)
Yuanming Zhang, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba
Clustered Software Queue for Efficient Pipelined Multithreading. PDCAT (2009)
Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba
Are Uniform Nerworks Scalable? PDCAT (2008)
Yuanming Zhang, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba
Clustered Decoupled Software Pipelining on Commodity CMP. ICPADS (2008)
Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba
Potentials of Branch Predictors: From Entropy Viewpoints. ARCS (2008)
Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba
Introducing entropies for representing program behavior and branch predictor performance. Experimental Computer Science (2007)
Kanemitsu Ootsu, Takahiko Kobayashi, Takashi Yokota, Takanobu Baba
A thread partitioning technique for multithreaded execution along hot paths. Parallel and Distributed Computing and Networks (2007)
Takashi Yokota, Masaaki Ogawa, Kanemitsu Ootsu, Takamitsu Baba
Quasi-global routing for fault-tolerant high-performance interconnection networks. Parallel and Distributed Computing and Networks (2007)
Takashi Yokota, Kanemitsu Ootsu, Fumihito Furukawa, Takanobu Baba
Entropy Throttling: A Physical Approach for Maximizing Packet Mobility in Interconnection Networks. Asia-Pacific Computer Systems Architecture Conference (2006)
Atsushi Tsukikawa, Fumihito Furukawa, Takayuki Aoki, Daisuke Oka, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba
Design and Implementation of a VLIW Processor Simulation Environment with Instruction Scheduling Framework. IASTED PDCS (2005)
Takashi Yokota, Moriyuki Saito, Fumihito Furukawa, Kanemitsu Ootsu, Takanobu Baba
Two-Path Limited Speculation Method for Static/Dynamic Optimization in Multithreaded Systems. PDCAT (2005)
Takashi Yokota, Masashi Nishitani, Kanemitsu Ootsu, Fumihito Furukawa, Takanobu Baba
Cross-Line - A Globally Adaptive Control Method of Interconnection Network. ISHPC (2005)
Yoshiyuki Iwamoto, Koichi Suga, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba
Receiving message prediction method. Parallel Comput. 29 (11-12) (2003)
Takashi Yokota, Masamichi Nagafuchi, Yoshito Mekada, Tsutomu Yoshinaga, Kanemitsu Ootsu, Takanobu Baba
Real-Time Medical Diagnosis on a Multiple FPGA-based System. FPL (2002)
Takashi Yokota, Masamichi Nagafuchi, Yoshito Mekada, Tsutomu Yoshinaga, Kanemitsu Ootsu, Takanobu Baba
A Scalable FPGA-Based Custom Computing Machine for a Medical Image Processing. FCCM (2002)
Kanemitsu Ootsu, Takafumi Ono, Takashi Yokota, Takanobu Baba
A Methodology of Binary-level Multithreading and Its Preliminary Evaluation. IASTED PDCS (2002)
Takashi Yokota, Hiroshi Matsuoka, Kazuaki Okamoto, Hideo Hirono, Shuichi Sakai
Virtual control channel and its application to the massively parallel computer RWC-1. HiPC (1997)
Kazuaki Okamoto, Shuichi Sakai, Hiroshi Matsuoka, Takashi Yokota, Hideo Hirono
Multithread execution mechanisms on RICA-1 for massively parallel computation. IEEE PACT (1996)
Shuichi Sakai, Yuetsu Kodama, Mitsuhisa Sato, Andrew Shaw, Hiroshi Matsuoka, Hideo Hirono, Kazuaki Okamoto, Takashi Yokota
Reduced Interprocessor-Communication Architecture and its Implementation on EM-4. Parallel Comput. 21 (5) (1995)
Atsushi Hori, Takashi Yokota, Yutaka Ishikawa, Shuichi Sakai, Hiroki Konaka, Munenori Maeda, Takashi Tomokiyo, Jörg Nolte, Hiroshi Matsuoka, Kazuaki Okamoto, Hideo Hirono
Time Space Sharing Scheduling and Architectural Support. JSSPP (1995)
Takashi Yokota, Hiroshi Matsuoka, Kazuaki Okamoto, Hideo Hirono, Atsushi Hori, Shuichi Sakai
A prototype router for the massively parallel computer RWC-1. ICCD (1995)
Shuichi Sakai, Hiroshi Matsuoka, Yuetsu Kodama, Mitsuhisa Sato, Andrew Shaw, Hideo Hirono, Kazuaki Okamoto, Takashi Yokota
RICA: Reduced Interprocessor-Communication Architecture - Concept and Mechanisms. SPDP (1993)
Takeshi Otsuka, Douglas Villaret, Takashi Yokota, Yutaka Takebe, Frank Lee, Naoko Arai, Ken-ichi Arai
Structural analysis of the mouse chromosomal gene encoding interleukin 4 which expresses B cell, T cell and mast cell stimulating activities. Nucleic Acids Res. 15 (1) (1987)
Takashi Yokota, Hideharu Amano, Hideo Aiso
Dynamic fault recovery in mesh-connected parallel computers. Systems and Computers in Japan 17 (7) (1986)