Katsuya Kikuchi

Publication Activity (10 Years)

Years Active: 2006-2021
Publications (10 Years): 15

Top Topics

Integrated Circuit

Chosen Plaintext

Malicious Nodes

Top Venues

Microelectron. Reliab.

IEICE Electron. Express

Publications

Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
Analysis and evaluation of noise coupling between through-silicon-vias. IEICE Electron. Express 18 (11) (2021)
Yuuki Araga, Ryo Kasai, Daisuke Tanaka, Yoshihide Murakami, Kyoshi Mihara, Kazuo Makida, Hiroki Sonoda, Makoto Nagata, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
Landside capacitor efficacy among multi-chip-module using Si-interposer. IEICE Electron. Express 18 (9) (2021)
Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. IEEE J. Solid State Circuits 55 (10) (2020)
Takuji Miki, Makoto Nagata, Akihiro Tsukioka, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs. 3DIC (2019)
Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
A Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. A-SSCC (2019)
Wei Feng, Naoya Watanabe, Haruo Shimamoto, Masahiro Aoyagi, Katsuya Kikuchi
Thermal Stress Comparison of Annular-Trench-Isolated (ATI) TSV with Cu and Solder Core. 3DIC (2019)
Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota, Katsuya Kikuchi, Masahiro Aoyagi
Designing Efficient Parallel Processing in 3D Standard-Chip Stacking System with Standard Bus. MCSoC (2017)
Samson Melamed, Naoya Watanabe, Shunsuke Nemoto, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi
Thermal impact of extreme die thinning in bump-bonded three-dimensional integrated circuits. Microelectron. Reliab. 79 (2017)
Wei Feng, Naoya Watanabe, Haruo Shimamoto, Masahiro Aoyagi, Katsuya Kikuchi
Validation of TSV thermo-mechanical simulation by stress measurement. Microelectron. Reliab. 59 (2016)
Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi, Hidekazu Kikuchi, Azusa Yanagisawa, Akio Nakamura
Wet cleaning process for high-yield via-last TSV formation. 3DIC (2016)
Wei Feng, Bui Thanh Tung, Naoya Watanabe, Haruo Shimamoto, Masahiro Aoyagi, Katsuya Kikuchi
Fabrication and stress analysis of annular-trench-isolated TSV. Microelectron. Reliab. 63 (2016)
Samson Melamed, Naoya Watanabe, Shunsuke Nemoto, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi
Impact of thinning stacked dies on the thermal resistance of bump-bonded three-dimensional integrated circuits. Microelectron. Reliab. 67 (2016)
Samson Melamed, Katsuya Kikuchi, Masahiro Aoyagi
Investigation of effects of metalization on heat spreading in bump-bonded 3D systems. 3DIC (2015)
Bui Thanh Tung, Naoya Watanabe, Masahiro Aoyagi, Katsuya Kikuchi
Twice-etched silicon approach for via-last through-silicon-via with a Parylene-HT liner. 3DIC (2015)
Samson Melamed, Fumito Imura, Hiroshi Nakagawa, Katsuya Kikuchi, Michiya Hagimoto, Yukoh Matsumoto, Masahiro Aoyagi
Impact of die thinning on the thermal performance of a central TSV bus in a 3D stacked circuit. Microelectron. J. 46 (12) (2015)
Bui Thanh Tung, Xiaojin Cheng, Naoya Watanabe, Fumiki Kato, Katsuya Kikuchi, Masahiro Aoyagi
Copper filled TSV formation with Parylene-HT insulator for low-temperature compatible 3D integration. 3DIC (2014)
Katsuya Kikuchi, Masahiro Aoyagi, Masaaki Ujiie, Shinya Takayama
Ultrawideband ultralow PDN impedance of decoupling capacitor embedded interposers using narrow gap chip parts mounting technology for 3-D integrated LSI system. 3DIC (2014)
Wei Feng, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi
Analysis of thermal stress distribution for TSV with novel structure. 3DIC (2014)
Katsuya Kikuchi, Fumiki Kato, Shunsuke Nemoto, Hiroshi Nakagawa, Masahiro Aoyagi, Youtaro Yasu, Kohji Koshiji
Investigation of optimized high-density flip-chip interconnect design including micro Au bumps for 3-D stacked LSI packaging. 3DIC (2013)
Masahiro Aoyagi, Naoya Watanabe, Motohiro Suzuki, Katsuya Kikuchi, Shunsuke Nemoto, Noriaki Arima, Misaki Ishizuka, Koji Suzuki, Toshio Shiomi
New optical three dimensional structure measurement method of cone shape micro bumps used for 3D LSI chip stacking. 3DIC (2013)
Katsuya Kikuchi, Chihiro Ueda, Fumiaki Fujii, Yutaka Akiyama, Naoya Watanabe, Yasuhiro Kitamura, Toshio Gomyo, Toshikazu Okubo, Tetsuya Koyama, Tadashi Kamada, Masahiro Aoyagi, Kanji Otsuka
PDN impedance analysis of TSV-decoupling capacitor embedded Silicon interposer for 3D-integrated CMOS image sensor system. 3DIC (2011)
Marco Chacin, Hiroyuki Uchida, Michiya Hagimoto, Takashi Miyazaki, Takeshi Ohkawa, Rimon Ikeno, Yukoh Matsumoto, Fumito Imura, Motohiro Suzuki, Katsuya Kikuchi, Hiroshi Nakagawa, Masahiro Aoyagi
COOL interconnect low power interconnection technology for scalable 3D LSI design. COOL Chips (2011)
Fumiki Kato, Katsuya Kikuchi, Hiroshi Nakagawa, Masahiro Aoyagi
Hot spots suppression by high thermal conductivity film in thin-sub strate CMOS ICs for 3D integration. 3DIC (2011)
Katsuya Kikuchi, Koichi Takemura, Chihiro Ueda, Osamu Shimada, Toshio Gomyo, Yukiharu Takeuchi, Toshikazu Okubo, Kazuhiro Baba, Masahiro Aoyagi, Toshio Sudo, Kanji Otsuka
Ultralow impedance evaluation system of wideband frequency for power distribution network of decoupling capacitor embedded substrates. 3DIC (2009)
Koichi Takemura, Katsuya Kikuchi, Chihiro Ueda, Kazuhiro Baba, Masahiro Aoyagi, Kanji Otsuka
SrTiO3 thin film decoupling capacitors on Si interposers for 3D system integration. 3DIC (2009)
Yasuhiro Yamaji, Tokihiko Yokoshima, Katsuya Kikuchi, Hiroshi Nakagawa, Masahiro Aoyagi
Chemical flip-chip bonding method for fabricating 10-µm-pad-pitch interconnect. IEICE Electron. Express 5 (18) (2008)
Junso Pak, Masahiro Aoyagi, Katsuya Kikuchi, Joungho Kim
Band-Stop Filter Effect of Power/Ground Plane on Through-Hole Signal Via in Multilayer PCB. IEICE Trans. Electron. (4) (2006)